2 1 century, mankind will enter the information society in an all-round way, and will constantly put forward higher development requirements for microelectronic information technology and microelectronic VLSI basic technology. Microelectronics technology will remain one of the most important and dynamic high-tech fields in 2 1 century. Integrated circuit (IC) technology plays an important role in the field of microelectronics. With the development of integrated circuit technology, electronic design automation EDA has gradually become an important design method, which is widely used in analog and digital circuit systems and many other fields.
VHDL is a widely used design input hardware language, which can be used for the description, simulation and automatic design of digital circuits and systems. CPLD/FPGA (Complex Programmable Logic Device/Field Programmable Gate Array) is flexible for the design of digital system, and it also has strings! Parallel working mode, high integration! High speed! High reliability and other obvious characteristics, CPLD/FPGA clock delay can reach nanosecond level, combined with its parallel working mode, it is widely used in ultra-high speed field and real-time measurement and control.
The purpose of this design is to design a special A/D converter controller using programmable logic devices to replace the ordinary microcontroller for data acquisition. Abstract: The data sampling control of A/D is introduced. This design needs a data acquisition system composed of CPLD/FPGA, ADC and LED display. CPLD/FPGA is used to realize A/D conversion, data operation and display control of relevant data in data acquisition. In addition to learning the corresponding hardware knowledge, this topic also needs to learn how to design programmable logic devices using VHDL language.
The future EDA technology will develop in breadth and depth.
(1) In terms of breadth, EDA technology will become more and more popular. In the past, due to its high price and high requirements for hardware environment, its operating environment was workstation and UNIX operating system. In recent years, EDA software platforms have developed rapidly, and EDA software on these PC platforms has a set of logic design, simulation and synthesis tools. With the improvement of PC performance, the software functions on PC platform will be more perfect.
(2) In terms of depth, the next step of EDA technology development is ESDA (Electronic System Design Automation) and CE (Concurrent Engineering Concurrent Design Project). At present, various EDA tools, such as system simulation, PCB wiring, logic synthesis and DSP design tools, are independent of each other. With the development of technology, all system tools need to work under a unified database and management framework, so the concepts of ESDA and concurrent engineering are put forward.
The second chapter is the development and application of EDA technology.
2. 1 Overview of Electronic Design Automation (EDA)
2. 1. 1 What is electronic design automation (EDA)?
In the field of electronic design technology, the application of programmable logic devices (such as PLD and GAL) has been well popularized. These devices bring great flexibility to the design of digital systems. Because this device can reconstruct its hardware structure and working mode through software programming, the hardware design can be as convenient and fast as the software design. All this has greatly changed the traditional digital system design method, design process and even design concept.
Electronic design automation (EDA) is a technology to realize the automatic design of electronic systems or electronic products. It is closely related to the development of electronic technology and microelectronics technology, absorbs most of the latest research results in the field of computer science, and develops from the concepts of CAD (Computer Aided Design), CAM (Computer Aided Manufacturing), CAT (Computer Aided Testing) and CAE (Computer Aided Engineering) in the early 1990s. EDA technology uses computer as a tool to automatically complete logic compilation, simplification, segmentation, synthesis and optimization, layout, simulation, adaptive compilation, logic mapping and program download of specific target chips on EDA software platform. The designer's work is limited to describing the hardware function of the system with the help of software. With the help of EDA tools and corresponding FPGA/CPLD devices, the final design result can be obtained. Although the target system is hardware, the whole design and modification process is as convenient and efficient as completing software design. Of course, the so-called EDA here mainly refers to the automatic design of digital systems, because the software and hardware technologies in this field are relatively mature and the application is relatively popular. However, the EDA of analog electronic system is becoming practical, and its original EDA tools do not necessarily need hardware description language. In addition, from the perspective of the breadth and depth of application, the digital system design technology based on EDA has a larger application market and more urgent demand because of the comprehensive digitization of the electronic information field.
2. The development history of1.2eda
The development of EDA technology began in 1970s and went through three stages. CAD (Computer Aided Design) of electronic circuit is the primary stage of EDA development and an important part of advanced EDA system. It helps engineers to design circuit diagrams, printed circuit boards and integrated circuit boards of electronic systems by using the graphics editing, analysis and storage capabilities of computers. Using two-dimensional graphic editing and analysis can mainly solve a lot of repetitive work in the later stage of electronic circuit design, which can reduce the tedious repetitive work of designers, but the degree of automation is low and the whole design process needs manual intervention. This kind of special software is mostly based on microcomputer, which is easy to learn and use, and the design of small and medium-sized electronic systems is reliable and effective. At present, many of these special softwares are still widely used in engineering design. In the early 1980s, EDA technology began to analyze the technical design process, and introduced EDA products with simulation (logic simulation, time sequence analysis and fault simulation) and automatic layout and routing as the core. At this stage, EDA introduced the latest achievements of a series of computer disciplines such as three-dimensional graphics technology, window technology, computer operating system, network data exchange, database and process management into electronic design, and formed CAE-computer aided engineering. The intermediate stage of EDA technology. Its main feature is that it has automatic layout and computer simulation, analysis and verification functions of circuits. Its function is not only to assist design, but also to take the place of people for some kind of thinking. CAE of EDA system based on schematic diagram is intuitive and easy to understand, but it is difficult to meet the requirements of complex electronic design and is not suitable for design optimization.
Therefore, based on automatic synthesizer and hardware description language, ESDA (Electronic System Design Automation) appeared in 1990s, that is, EDA stage, which is often called EDA now. In the past, the traditional design method of electronic products in electronic systems was to use bottom-up procedures. Designers first divided the system structure into blocks and directly designed the circuit level. This design method makes it impossible for designers to predict the problems in the next stage, and whether there are problems in each stage is often determined when the whole system is debugged. It is also difficult to make the whole system achieve the established functions and indicators through the adjustment of local circuits, and the success of the design cannot be guaranteed. In the advanced stage of EDA technology, a new design concept is adopted: top-down design program and concurrent engineering design method. The designer's energy mainly focuses on the accurate definition of the required electronic products, and EDA system completes the design of electronic products from system level to physical level. At present, the main feature of EDA technology is to support high-level language description system, and the theory of high-level synthesis has been greatly developed, which can be used for system-level simulation and synthesis. Figure 2- 1 is a schematic diagram of the above three stages.
Figure 2-2- 1 EDA development stage schematic diagram
2. Application of1.3 EDA
With the continuous development of large-scale integrated circuit technology and computer technology, the content of EDA technology is increasing at an alarming rate in the design of electronic systems involving communication, national defense, aerospace, medicine, industrial automation, computer applications, instrumentation and other fields; The development of electronic high-tech projects also depends on the application of EDA technology. Even in the development of ordinary electronic products, EDA technology often makes some original technical bottlenecks easily broken through, thus greatly shortening the product development cycle and greatly improving the cost performance. It goes without saying that EDA technology will soon become an extremely important part in the field of electronic design.
Electronic design experts believe that the era of single chip microcomputer has passed, and the future will be the era of EDA, which is very insightful. With the rapid progress of microelectronics technology, electronics has entered a new era. Its characteristic is that the application of electronic technology has penetrated into all walks of life at an unprecedented scale and speed. The demand for the design of application specific integrated circuits (ASIC) is more and more urgent in all walks of life. The wide application of field programmable devices provides technical and material conditions for electronic system design engineers in various industries to develop their own ASIC. Compared with the development of single chip microcomputer system, the development of FPGA/CPLD by EDA technology is usually pure hardware development in the form of software, and special ASIC can be developed in this way. The final ASIC chip can be FPGA/ CPLD or mask chip of autocratic gate array, and FPGA/CPLD plays the role of hardware simulation ASIC chip.
2.2 FPGA/ CPLD development based on EDA
Nowadays, the development of electronic design technology in China will face a more important breakthrough, that is, the wide application of FPGA/CPLD (Field Programmable Gate Array/Complex Programmable Logic Device) based on EDA. In a sense, the physical mechanism of the new electronic system will return to the original pure digital circuit structure, but this is a higher-level cycle, which accommodates the excellent parts of the past digital technology at a higher level, sublates the MCU system, and has made a qualitative leap in the technical operation and system composition of electronic design. If MCU is infinite in logic realization, then FPGA/CPLD not only contains the characteristics of MCU, but also touches the physical limit of silicon chip circuit, and has many characteristics such as serial-parallel working mode, high speed, high reliability and wide aperture applicability. Moreover, with the development of EDA technology and the progress of FPGA/CPLD in the deep submicron field, the physical and functional boundaries between them and independent devices such as MCU, MPU, DSP, A/D, D/A, RAM and ROM have become increasingly blurred. Especially soft/hard IP chips (intellectual property chips; With the rapid development of the core industry of intellectual property (circuit design with registered property rights), embedded general-purpose and standard FPGA devices stand out, and system-on-a-chip (SOC) is close at hand. With the rise of IP chip industry with the characteristics of knowledge economy, FPGA/CPLD has attracted more and more attention from people in the industry because of its irreplaceable position.
2.2. Introduction of1FPGA/CPLD
Both FPGA and CPLD are high-density field programmable logic chips, which can integrate a large number of logic functions into a monolithic integrated circuit, and its integration level has now developed to one million gates. Complex programmable logic device CPLD is developed from PAL (Programmable Array Logic) or GAL (generic array logic). It uses global metal interconnects, so it has great delay predictability and is easy to control sequential logic. But the power consumption is relatively large. Field programmable gate array (FPGA) is evolved from programmable gate array (MPGA) and programmable logic device, which combines their characteristics. Therefore, FPGA not only has the high logic density and universality of gate array, but also has the user programmable characteristics of programmable logic device. FPGA is usually composed of programmable logic units (or macro units) separated by wiring resources, and the whole chip is composed of programmable Ir0 units around the array. Its internal resources are interconnected in segments, so the delay is unpredictable and can only be measured after programming.
There are three programming techniques for establishing internal programmable logic connection between CPLD and FPGA: devices based on anti-fuse technology are only allowed to be programmed once and cannot be modified after programming. Its advantages are high integration, high working frequency and good reliability, and it is suitable for harsh environment with strong electromagnetic radiation interference. The programmable logic chip based on EEPROM storage technology can be repeatedly programmed 100 times, and the programming information will not be lost after the system is powered off. Programming methods are divided into programming on the programmer and programming with download line. For devices programmed by downloading cables, as long as the devices are soldered on the printed circuit board first, the standard 5V, 3.3V or 2.5V logic level signals used for programming can be generated by PC, SUN workstation, ATE (Automatic Tester) or embedded microprocessor system, which is also called ISP (Programmable in System) programming, and its debugging and maintenance are also very convenient. The device programming data based on SRAM technology is stored in the RAM area of the device, which makes it have the function designed by users. When the system is not powered on, the programming data is stored in EPROM, hard disk or floppy disk. When the system is powered on, these programming data are immediately written into programmable devices, thus realizing dynamic configuration at board level or system level.
2.2.2 FPGA/CPLD development process based on EDA tools.
Development process of FPGA/CPLD: At the beginning of design, the designer's design intention is expressed in words (such as VHDL, Verilog-HDL program) or graphics (schematic diagram, state diagram, etc.). ) by using the text or graphic editor of EDA tools. After the design description is completed, it can be debugged and compiled by a compiler and turned into a specific text format for the next comprehensive preparation. Here, for most EDA software, which input form is adopted in the initial design is optional or mixed. The general schematic diagram input mode is relatively easy to master, intuitive and convenient. The circuit schematic diagram drawn (please note that this schematic diagram is essentially different from that drawn by PROTEL) is exactly the same as the traditional device connection method and is easily accepted. Moreover, there are many ready-made unit devices available in the editor, and you can also design components according to your own needs (the functions of components can be expressed by HDL or schematic diagram). Of course, the most common input method is the text mode of HDL program. This method is the most common. If the compiled file is a standard VHDL file, the described content can be simulated before synthesis, which is called behavior simulation. That is, send the designed source program directly to VHDL simulator for simulation. Because the simulation at this time is only based on the semantics of VHDL and has nothing to do with the specific circuit. In the simulation, we can give full play to the statements suitable for simulation control in VHDL. This simulation process is very necessary for the design of large-scale circuit systems, but generally speaking, this step can be omitted.
Figure 2-2 Development Process of FPGA/CPLD
The third step of design is synthesis, which links software design with hardware implementation, which is the key step to transform software into hardware circuit. The synthesizer synthesizes the source file for the product series of an FPGA/CPLD supplier, so the synthesis result is hardware-realizable. After synthesis, HDL synthesizer can generally generate netlist files in EDIF, XNF or VHDL format, and describe the most basic door structure from the door level. Some EDA software has the function of drawing netlist files into different levels of circuit diagrams for designers to use. After synthesis, the generated netlist file can be used for functional simulation, so as to understand the consistency between design description and design intention. Functional simulation only tests and simulates the logical functions described in the design to find out whether the realized functions meet the requirements of the original design, and the simulation process does not involve the hardware characteristics of specific devices, such as delay characteristics. General design, this level of simulation can also be omitted. After synthesis, FPGA/CPLD layout/routing adapter must be used to logically map the synthesized netlist file to specific target devices, including bottom device configuration, logic division, logic optimization, layout and routing. After the adaptation is completed, EDA software will produce many results for the design: 1 adaptation report: the contents include the allocation and utilization of resources in the chip, pin locking, Boolean equation description of the design, etc. 2. Netlist file of time series simulation; 3 download files, such as JED or POF files; 4 adaptation error report, etc. Timing simulation is a kind of simulation close to the real device operation, and the hardware characteristics of the device have been considered in the simulation process, so the simulation accuracy is much higher. The netlist file of time series simulation contains more accurate delay information. If all the above processes, including compilation, synthesis, wiring/adaptation and behavior simulation, function simulation and timing simulation, have not found any problems, that is, they meet the requirements of the original design, then the configuration/download file generated by the adapter can be loaded into the target chip FPGA or CPLD through the FPGA/CPLD programmer or download line, and then the last step shown in figure 1-2: hardware simulation or testing, so as to be in a more realistic environment. The so-called hardware simulation here is designed for ASIC. In ASIC design, the common method is to test the function of the system with FPGA, and then realize its VHDL design in ASIC form after passing; Hardware testing is aimed at the direct application of FPGA or CPLD in circuit system testing.
2.2.3 Advantages and disadvantages of development with FPGA/CPLD
We believe that the development and application of FPGA/CPLD devices based on EDA technology can fundamentally solve the problems encountered by MCU. Compared with MCU, the advantages of FPGA/CPLD are various and the most basic:
1. The programming mode is simple and advanced. FPGA/CPLD products increasingly adopt advanced IEEE1149.1Boundary Scan Test (BST) technology (developed by JTAG) and ISP (programming in system configuration). At the working level of +5V, the whole or part of FPGA/CPLD on the working system can be programmed at any time, and the so-called daisy-chain multi-chip serial programming can be carried out. For FPGA with SRAM structure, there is almost no limit to the number of times of downloading and programming (such as FLEXI 10K series of Altera). This programming method can easily realize infrared programming, ultrasonic programming or wireless programming, or remote online programming through telephone lines. These functions have special uses in industrial control, intelligent instrumentation, communication and military affairs.
2. High speed. The clock delay of FPGA/CPLD can reach nanosecond level. Combined with its parallel working mode, it has a very broad application prospect in ultra-high speed application and real-time measurement and control.
3. High reliability. In the field of high reliability application, the shortcomings of single chip microcomputer leave a lot of room for the application of FPGA/CPLD. The high reliability of FPGA/CPLD is not only the inherent defects such as unreliable MCU reset and PC deviation, but also that the whole system can be downloaded to the same chip, thus greatly reducing the size and facilitating management and shielding.
4. Development tools and design languages are standardized, and the development cycle is short. Because the integration scale of FPGA/CPLD is very large, the integration level can reach one million gates. Therefore, the design and development of FPGA/ CPLD must use powerful EDA tools to design electronic systems and develop products through hardware description languages (such as VHDL or Verilog-HDL) that meet international standards. Because of the universality of development tools, standardization of design language and design flow, it has almost nothing to do with the hardware structure of FPGA/ CPLD devices used.
Therefore, all kinds of successfully designed logic function block software have good compatibility and portability, which can be used in almost any type of FPGA/ CPLD, and can also be registered as so-called IP chips through intellectual property confirmation, thus greatly improving the product design efficiency of the system on chip. Because the corresponding EDA software has perfect and powerful functions, convenient real-time simulation mode, vivid and intuitive development process, and involves few hardware factors, it can complete very complicated system design in a short time, which is the most valuable feature of products entering the market quickly. American TI Company believes that 80% of the functions of an ASIC can be synthesized by ready-made logic such as IP chips. EDA experts predict that the FPGA/CPLD design of large-scale systems in the future will only be the assembly of various multiplexing logic and IP chips, and its design cycle will take at least a few minutes.
5. Powerful function and wide application. At present, the choice of FPGA/ CPLD is very wide, and chips with different capacities can be selected according to different applications. Using them, almost any form of digital circuit or digital system can be designed. With the wide application of such devices and the sharp drop in cost, the direct application rate of FPGA/CPLD in the system is approaching the development of ASIC. At the same time, the design method of FPGA/CPLD also has its limitations. This is mainly reflected in the following points:
(1). General FPGA/CPLD design software needs to optimize the logic of the circuit ((logic synthesis &; Optimization), in order to get the result that is easy to realize, therefore, there are some differences between the final design and the original design in logic implementation and time delay. Therefore, some circuit forms often used in traditional design methods (especially some asynchronous sequential circuits) are not suitable for FPGA/CPLD design methods. This requires designers to know more about the characteristics of FPGA/CPLD design software in order to get an optimized design.
(2) FPGA generally adopts lookup table (LUT) structure (Xilinx), AND-OR structure (Altera) or multiplexer structure (Actel). The advantage of these structures is programmable, but the disadvantage is that the delay is too large, which causes the timing shift between synchronous signals in the original design. At the same time, if the circuit is large, it needs to be divided. Due to the derived delay time, the delay time and timing offset are even larger. Time delay is a common problem in ASIC design. It is very difficult to accurately control the delay of the circuit, especially in programmable logic such as FPGA/CPLD.
(3) The capacity of 3)FPGA/CPLD and the number of I/O are limited. Therefore, a large circuit can only be realized by multiple FPGA/CPLD chips after logical division, and the division algorithm directly affects the design performance.
(4) Due to the high cost of modifying the PCB of the target system, users generally want to modify the circuit on the premise that the lead distribution is fixed. However, when the chip utilization rate is improved, or there are many I/O terminals on the chip, small modifications will often reduce the chip circulation rate;
(5) Early FPGA chips could not realize some special circuits such as memory and analog circuits. Some of the latest FPGA products have integrated the general RAM structure. However, this structure is either inefficient or can not fully meet the needs of designers. This contradiction comes from the structural limitation of FPGA itself, which is difficult to solve in a short time.
6. Although FPGA has realized the hardware simulation of ASIC design, the delay characteristics of FPGA are different from traditional ASIC forms such as gate array and standard cell, so when switching FPGA design to other ASIC designs, there is still the possibility of design failure due to delay mismatch. In order to solve this problem, an ASIC hardware simulation system using FPGA array (such as the hardware simulation system of Quicktum Company) has appeared in the world. The special hardware simulation system adopts the method of combining software and hardware, realizes the rapid prototype of ASIC with FPGA array, and connects it to the system for testing. The system can accept designated test points and can be directly observed in FPGA array (just like in software simulation), so the accuracy and efficiency of simulation are greatly improved.
2.3 Hardware Description Language
Hardware Description Language (HDL) is relative to common computer software languages such as C and Pascal. HDL is a computer language used to design hardware electronic systems, which describes the logic function, circuit structure and connection mode of electronic systems. Designers can use HDL programs to describe the required circuit system and specify its structural characteristics and circuit behavior. Then, the synthesizer and adapter are used to turn this program into a gate-level or lower-level structured netlist file and download file, which can control the internal structure of FPGA and CPLD and realize the corresponding logical functions. The hardware description language has the following advantages: A. The design technology is complete, the method is flexible and the support is extensive. B, speed up the design cycle of hardware circuits and reduce the design difficulty of hardware circuits. C. Using early system simulation, problems can be found and eliminated in early system design. Language design can be independent of process technology. E language standards and specifications, which are easy to share and reuse with * * * *. As far as the development of FPGA/CPLD is concerned, VHDL language is one of the most commonly used and popular hardware description languages. This design chooses VHDL language, and the following will mainly introduce VHDL language.
2.3. 1 VHDL language introduction
VHDL is the abbreviation of English prefix of ultra-high speed integrated circuit hardware description language, and the full name of English is ultra-high speed integrated circuit hardware description language. It was developed by the VHSIC (Ultra High Speed Integrated Circuit) project funded by the US Department of Defense in the 1970s and 1980s, and was born in 1982. At the end of 1987, VHDL was recognized as the standard hardware description language by IEEE (Institute of Electrical and Electronics Engineers). Since IEEE published the standard version of VHDL (IEEE std 1076- 1987 standard), various EDA companies have successively launched their own VHDL design environments. Since then, VHDL has been widely accepted in the field of electronic design and gradually replaced the original non-standard HDL. 1993, IEEE revised VHDL, expanded the content of VHDL from a higher level of abstraction and system description ability, and released new versions of VHDL, namely ANSI/IEEE std 1076 and 1993. 1996 IEEE 1076.3 became the comprehensive standard of VHDL.
VHDL is mainly used to describe the structure, behavior, function and interface of digital system, which is very suitable for the application design of programmable logic chips. Compared with other HDL, VHDL has stronger behavior description ability, which determines that it becomes the best hardware description language in the field of system design. Strong behavior description ability is an important guarantee for describing and designing large-scale electronic systems from logical behavior without specific device structure. As far as popular EDA tools and VHDL synthesizers are concerned, it is no longer a problem to synthesize VHDL programs based on abstract behavior description style into specific netlist files of target devices such as FPGA and CPLD.
VHDL language will play the same role in hardware design as C and C++ in software design. In the design of large-scale digital system, it will gradually replace the low-level and tedious hardware description methods such as logic state table and logic circuit diagram, and become the main hardware description tool. It will become a language that all technicians in the field of digital system design must master. The combination of VHDL and programmable logic devices, as a powerful design method, will bring a record speed for designers' products to market.
2.3.2 VHDL language design steps
Using VHDL language to design can be divided into the following steps:
1. Definition of design requirements. Before designing and writing VHDL code, you must clearly understand your design purpose and requirements. For example, what function do you want to design? Clear definition of required signal setup time, clock/output time, maximum system operating frequency, critical path, etc. It will be helpful for your design, and then choose the appropriate design method and the corresponding device structure for design synthesis.
2. Use VHDL language to describe the design.
(1) The design method should be determined. Generally speaking, there are three design methods: top-down design, bottom-up design and flat design.
The first two ways include the generation of design levels, while the latter way regards the described circuit as a single module circuit. The top-down approach requires that your design be divided into different functional components, each of which has specially defined inputs and outputs and performs special logical functions. Firstly, a top-level module composed of interconnected functional elements is generated and made into a netlist, and then each element in it is designed. The bottom-up approach is just the opposite. Flat design means that all functional components are designed in detail on the same floor and drawing.
(2) Write the design code. Writing VHDL code is very different from writing code in other computer programming languages. You must clearly realize that you are designing hardware, and the written VHDL code must be able to be integrated into the digital logic realized by programmable logic devices. Understanding the general workflow of simulation software and comprehensive software in EDA tools is helpful to write excellent codes.
3. Simulate the function of VHDL original code with VHDL simulator. For large-scale design, using VHDL simulation software can save time, and can find mistakes in the design in the early stage of design, so as to correct them, thus minimizing the impact on the design progress. Because for large-scale design, its comprehensive optimization and configuration often take several hours. Simulating the original code before synthesis can greatly reduce the number and time of design repetition and error correction. But for small designs, it is often not necessary to simulate the original VHDL code first, even if it is done, it is of little significance. Because for a small design, it takes little time to fully optimize and configure, and after comprehensive optimization, you will often find that you will need to modify your design in order to achieve performance goals. In this case, it is meaningless for users to spend time on the original code simulation in advance, because once the design is changed, it must be simulated again.
4. Using VHDL comprehensive optimization software to optimize the original VHDL code. After selecting the target device and inputting the constraint conditions, the VHDL comprehensive optimization software tool will process the VHDL original code, generate the optimized network table, and make a rough timing simulation. The general processing flow of comprehensive optimization software tools is as follows: first, detect grammatical and semantic errors; Then, after comprehensive processing, a set of logic equations of specific process will be obtained for CPLD devices, and a netlist of specific process will be obtained for FPGA devices. Finally, optimize. The optimization of CPLD usually includes simplifying logic to the minimum sum of product terms and reducing the number of logic block inputs required for any given expression. These equations are further optimized by the device to achieve resource allocation. The optimization of FPGA usually needs to express logic by the sum of product terms. The equation system can be decomposed based on the guidance of device-specific resources and driving optimization objectives. The decomposed factors can be used to evaluate the effectiveness of implementation, and its criteria can be used to decide whether to decompose other program systems differently or keep existing factors. Criterion usually refers to the ability to share the same factor, that is, it can be temporarily stored for comparison with any newly generated factor.
5. configuration. The optimized network table obtained after comprehensive optimization is placed in the CPLD or FPGA target device selected earlier. This process is called configuration. Optimizing