Samsung said on Thursday that it expects to start mass production this quarter, in the coming weeks, using its 3GAE (3nm Gate All-in-Early) manufacturing process. The announcement not only marks the industry's first 3nm-level manufacturing technology, but also the first node to use gate-all-around field-effect transistors (GAAFETs).
Samsung wrote in its financial statement: "Exceeding market growth by sustaining leadership in GAA process technology, adopting pricing strategies to ensure future investments, and raise the yield and portion of our advanced process)
Samsung’s 3GAE process technology is the company’s first process to use GAA transistors, and Samsung officially calls it a multi-bridge trench field effect transistor (MBCFET).
Samsung officially launched its 3GAE and 3GAP nodes about three years ago. Samsung says the process will achieve 30% better performance, 50% lower power consumption, and up to 80% higher transistor density (including a mix of logic and SRAM transistors). It remains to be seen how Samsung's actual combination of performance and power consumption will play out, though.
In theory, GAAFETs offer many advantages over the FinFETs currently in use. In a GAA transistor, the channel is horizontal and surrounded by the gate. GAA channels are formed using epitaxy and selective material removal, which allows designers to precisely tune transistor channels by adjusting their width. High performance is achieved through wider channels and low power consumption is achieved through narrower channels. This precision greatly reduces transistor leakage current (i.e., reduces power consumption) as well as transistor performance variability (assuming everything works properly), which means faster product delivery, time to market, and higher yields. In addition, according to a recent report from Applied Materials, GAAFET is expected to reduce cell area by 20 to 30%.
Speaking of applications, its recently launched IMS (Integrated Materials Solutions) system, a high-vacuum system for forming gate oxide stacks, aims to solve a major challenge in GAA transistor manufacturing, namely the channel. The space between them is very thin and the necessity of depositing polysilicon. A layer of gate oxide and a metal gate stack are formed around the channel in a very short time. Applied Materials' new AMS tool can deposit gate oxide as thin as 1.5 angstroms using atomic layer deposition (ALD), thermal steps and plasma processing steps. The highly integrated machine also performs all necessary metering steps.
Samsung's 3GAE is an "early" 3nm-level manufacturing technology, 3GAE will be used primarily by Samsung LSI (Samsung's chip development arm) and perhaps one or two SF's other alpha customers. Keeping in mind that Samsung's LSI and other early customers of SF tend to manufacture chips in high volumes, 3GAE technology is expected to see fairly widespread adoption, assuming the yields and performance of these products live up to expectations.
Transitioning to an entirely new transistor architecture is often a risk because it involves entirely new manufacturing processes as well as entirely new tools. Other challenges are the new layout methods, floorplanning rules, and routing rules introduced by all new nodes and addressed by new electronic design automation (EDA) software. Finally, chip designers need to develop entirely new IP, which is expensive.
Foreign media: Samsung’s 3nm yield rate is only 20
According to foreign media Phonearena, Samsung foundry is the world’s second largest independent foundry after giant TSMC. In other words, in addition to manufacturing Exynos chips of its own design, Samsung also builds chips based on designs submitted by third-party companies that are foundry customers like Qualcomm.
The Snapdragon 865 application processor (AP) is built by TSMC using its 7nm process node. When it comes to the 5nm Snapdragon 888 chipset, Qualcomm has returned to Samsung and continues to rely on Korean foundries to produce the 4nm Snapdragon 8 Gen 1. This is the AP that currently powers high-end Android phones made by Samsung, Xiaomi, and Motorola.
But in February, it was reported that Samsung Foundry’s yield on its 4nm process node was only 35. This means that only 35 of the chip die cut from the wafer can pass quality control. In comparison, TSMC achieved a yield of 70 when producing the 4nm Snapdragon 8 Gen 1 Plus. In other words, all things being equal, TSMC manufactured twice as many chips as Samsung during the same period.
This resulted in TSMC finally receiving an order from Qualcomm to build its remaining Snapdragon 8 Gen1 chipsets as well as the Snapdragon 8 Gen 1 Plus SoC. We also assume that TSMC will get the license to make the 3nm Snapdragon 8 Gen 2, even if Qualcomm needs to pay a premium to TSMC to have the chipset's exclusive manufacturer make enough chips in a short period of time.
Although Samsung has recently said that its production has been improving, a report from the Business Post claims that Samsung's 3nm process node production is still well below the company's goals. While the Samsung foundry's gate-all-around (GAA) transistor architecture debuted at its 3nm node, putting it ahead of TSMC (which will launch its GAA architecture at its 2nm node), the Samsung foundry's early 3nm Yields in nano production have always been in the 10 to 20 range.
Not only is this an extremely low yield that Samsung needs to improve on, it's even worse than the aforementioned 35 yield that Sammy experienced with the 4nm Snapdragon 8 Gen 1.
Wccftech says that the first "performance version" of the 3nm GAA chipset that Samsung will ship to customers starting next year may actually be a new in-house Exynos chip, according to sources. Samsung has reportedly been developing a new line of Exynos chips for its smartphones, but it's unclear at this stage whether they will be manufactured using the 3nm GAA process node.
TSMC and Samsung will soon have new challengers, as Intel has said it aims to take over the industry's process leadership by the end of 2024. It was also the first to acquire more advanced extreme ultraviolet (EUV) lithography machines.
Second-generation EUV machines are called High NA or high numerical aperture. The current EUV machine has an NA of 0.33, but the new machine has an NA of 0.55. The higher the NA, the higher the resolution of the circuit pattern etched on the wafer. This will help chip designers and foundries create new chipsets that contain even more transistors than the billions currently used on integrated circuits.
It would also prevent foundries from running wafers through EUV machines again to add additional features to the chips.
ASML says the higher-resolution patterns produced by second-generation EUV machines will provide improved resolution that will make chip features 1.7 times smaller and increase chip density by 2.9 times.
By getting this machine first, Intel will be able to take a big step toward its goal of regaining process leadership from TSMC and Samsung.
TSMC’s 3nm production time is exposed
According to Taiwan media Lianhe Daily, in the three-power competition for hegemony in wafer foundries, TSMC and Samsung are competing in 3nm, which has always attracted the attention of the global semiconductor industry. . According to the investigation, due to delays in the development schedule, Apple's new generation processor this year still uses TSMC's 3nm enhanced version of 5nm N4P, which has recently achieved a major breakthrough. TSMC has decided to take the lead in using the second version of the 3nm process N3B this year. In August this year, it will be simultaneously launched in the north and south of this year, namely the eighth phase of the R&D center of the Hsinchu factory 12 and the P5 factory of the Nanke 18 factory, officially using fin field effect batteries. Crystal (FinFET) architecture versus Samsung’s gate-around (GAA) process.
According to TSMC, the company’s 3-nanometer (N3) process technology will be another full-generation process after the 5-nanometer (N5) process technology. When the N3 process technology is launched, it will be the most advanced in the industry. Process technology, with the best PPA and transistor technology. Compared with N5 process technology, the logic density of N3 process technology will increase by about 70%, the speed will increase by 10-15% at the same power consumption, or the power consumption will be reduced by 25-30% at the same speed. The development progress of N3 process technology is in line with expectations and is progressing well. In the future, it will provide a complete platform to support mobile communications and high-performance computing applications. It is expected to receive product launches from multiple customers in 2021. In addition, mass production is expected to begin in the second half of 2022.
As mentioned above, Wafer Factory 18 will be TSMC’s main 3nm production plant. According to the data, TSMC Nanke’s Fab 18 is the current focus of production expansion. It has P1 P4*** 4 5nm and 4nm fabs, and P5 P8*** 4 3nm fabs, and P1 P3 Fab 18A is in mass production. As for the Fab 18B factory production line of P4 and P6, it has been completed. The Fab 18B factory, the 3-nanometer process production line, has started rolling out test chips as early as the end of last year. .
While chip design companies are still "fighting openly and covertly" for production capacity, the wafer manufacturing field is another story. For wafer manufacturing plants, what is more important now is the breakthrough of 3nm. Whoever takes the lead in mass-producing 3nm will occupy the commanding heights of the future wafer manufacturing industry and even affect the product roadmaps of chip giants such as AMD and Nvidia.
There is no doubt that at the 3nm node, currently only TSMC and Samsung can compete, but Intel is obviously also making efforts in advanced processes. However, judging from recent news, both TSMC and Samsung are having troubles in mass production of 3nm. Gartner analyst Samuel Wang said the ramp to 3nm will take longer than previous nodes.
TSMC is reportedly having trouble with yields on its 3nm process, according to a report citing semiconductor industry sources. The key rumor reported by sources is that TSMC is finding it difficult to achieve satisfactory yields on its 3nm FinFET process. But so far, TSMC has not publicly acknowledged any N3 delays, instead claiming that "good progress is being made."
As we all know, TSMC 3nm adopts Fin Field Effect Transistor (FinFET) structure in transistors. FinFET uses a three-dimensional structure to increase the contact area of ??the circuit gate, thereby making the circuit more stable, and at the same time achieving The goal of continued shrinkage of semiconductor manufacturing processes.
In fact, FinFET transistors are more or less at their limit at 3nm. Going further down will encounter physical limit problems such as current control leakage caused by process shrinkage. A large part of the reason why TSMC still chooses it is that it does not need to change too much. With more production tools, you can also have a more advantageous cost structure. Especially for customers, it can reduce production costs without having to make too many design changes. It can be said to be a win-win situation.
Previous public data shows that compared with 5nm chips, the logic density of TSMC's 3nm chips will be increased by 75%, the efficiency will be increased by 15%, and the power consumption will be reduced by 30%. It is reported that TSMC’s 3nm process has begun risk trial production and small-volume delivery in March 2021, and is expected to begin commercial production in the second half of 2022.
From a factory perspective, Phases 4 to 6 of Taiwan Nanke 18 Factory are TSMC’s 3nm mass production base. In terms of customers, as can be seen from the above, Intel, Apple, Qualcomm, etc. have all chosen TSMC. Morgan Stanley analyst Charlie Chan recently issued a report stating that TSMC will have an almost monopoly in the 3nm chip foundry market in 2023, with a market share of close to 100%.
Unlike TSMC’s yield problems, Samsung’s difficulty with 3nm is that it lags behind in the number of patented IP established on the 3nm GAA process. According to South Korean media reports, Samsung is disturbed by its lack of patents related to the 3-nanometer GAA process.
Samsung uses a gate-all-around (GAA) transistor architecture for transistors. Compared with TSMC's FinFET transistors, the cost of 3nm technology based on GAA is definitely higher, but from a performance perspective, transistors based on GAA architecture can provide better electrostatic characteristics than FinFET and meet certain pole width requirements, which can be expressed as Under the same process, the chip size can be made smaller using the GAA architecture.
Planar transistors, FinFETs and GAA FETs
Compared with the 5nm manufacturing process, Samsung’s 3nm GAA technology has improved the logic area efficiency by more than 35%, reduced power consumption by 50%, and improved performance. Got about 30. Samsung officially announced in June last year that the 3nm process technology had been successfully taped out. In addition, Samsung has also announced that it will launch an early version of 3nm GAA in 2022, and its "performance version" will ship in 2023.
Currently, in terms of factories, it has been reported that Samsung may invest US$17 billion in building a 3nm chip production line in the United States. In terms of customers, Samsung has not disclosed specifically, but there has been news that TSMC’s heavyweight customers such as Qualcomm and AMD are interested in importing Samsung’s 3nm process. However, due to the Korean media mentioned above, Qualcomm has already Work orders are handed over to TSMC, but Samsung’s 3nm customers are still a mystery.
After Pat Gelsinger took over as Intel CEO last year, the IDM giant that once tested the waters in the foundry field has returned to this market. At the same time, they also put forward very ambitious ambitions.
At the investor meeting on the 18th of this month, Intel CEO Pat Gelsinger once again emphasized that Intel’s 2nm process will be ready for mass production in the first half of 2024. This mass production time is earlier than TSMC, which means that the chip will be ready two years later. The competition between foundry business and TSMC will become more intense.
Although Intel has not disclosed too much about the 3nm process, Digitimes’ research report last year analyzed the transistor density of four manufacturers, TSMC, Samsung, Intel and IBM, on the same named semiconductor process node. question, and compared the transistor density of each company at 10nm, 7nm, 5nm, 3nm and 2nm.
In terms of factories, Intel has emphasized that it will spend 80 billion euros to set up factories in Europe. Christin Eisenschmid, Intel’s head of Germany, revealed in an interview that 2nm or smaller chips will be produced in Europe. Intel regards 2nm as an important key to expanding European production capabilities to avoid falling behind in the competition of advanced technologies in the future.
Generally speaking, at the 3nm node, only time will tell who will be the final winner among TSMC, Samsung and Intel, but judging from the current situation, TSMC may be slightly better.
3nm has reached the physical limit of Moore’s Law. How will it develop in the future? This has become a solution that researchers around the world are eager to seek. Currently, researchers are mostly trying to find solutions in transistor technology and materials.
The above-mentioned GAA transistor used by Samsung in the 3nm process is a good choice after 3nm. The GAA design channel has gates around the four sides, which can reduce the leakage voltage and improve the control of the channel. This is Key when scaling down process nodes. According to reports, TSMC will also use GAA transistors in the 2nm process.
Nanowires are nanostructures with diameters on the order of nanometers. One of the fundamental attractions of nanowire technology is that they exhibit powerful electrical properties, including high electron mobility due to their efficient one-dimensional structure.
Recently, researchers from HZDR announced that they have experimentally proven long-standing theoretical predictions about nanowires under tension. In their experiments, the researchers created nanowires composed of a GaAs core and an indium arsenide-aluminum shell. In the end, the results showed that the researchers could indeed increase the electron mobility of the nanowires by applying tensile strain to them. The relative mobility increase of approximately 30 was measured for unstrained nanowires and bulk GaAs. The researchers believe they can achieve even more dramatic increases in materials with larger lattice mismatches.
Recently, Intel’s technology patent on “stacked forksheet transistors” has attracted people’s attention.
Intel said the new transistor design could eventually enable a 3D and vertically stacked CMOS architecture that allows for an increased number of transistors compared to current state-of-the-art tri-gate transistors. In the patent, Intel describes the use of nanoribbon transistors and germanium films, which will act as dielectric isolation walls that are repeated in each vertically stacked layer of transistors, ultimately depending on how many transistors are stacked on top of each other.
It is understood that Intel is not the first company to use this manufacturing method. The Belgian research group Imec proposed this method in 2019. According to Imec’s first standard unit simulation results, when applied At the 2nm technology node, this technology can significantly increase transistor density compared to traditional nanosheet methods.
Vertical Transfer Field Effect Transistor (VTFET), jointly announced by IBM and Samsung, aims to replace the FinFET technology currently used in some of today's most advanced chips. The new technology will stack transistors vertically, allowing current to flow up and down the transistor stack, rather than laying the transistors flat on the surface of the silicon and allowing current to flow from one side to the other as is currently used on most chips.
According to IBM and Samsung, this design has two advantages. First, it would allow many performance limitations to be bypassed, extending Moore's Law beyond the 1-nanometer threshold. The contact points between them can also be influenced to increase current flow and save energy. They said the design could potentially double performance or reduce energy consumption by 85%.
In fact, for how advanced processes will evolve after 3nm, transistor manufacturing is only part of the solution. Chip design is also crucial, requiring on-chip interconnection, assembly and packaging, etc. to minimize the impact on device and system performance. lowest.
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