Samsung wrote in its financial statement: "Enhance its leading position in technology through the world's first large-scale production of GAA 3 nanotechnology." (By keeping the leading position of GAA process technology to surpass the market growth, adopt pricing strategy to ensure future investment, and increase the output and share of our advanced processes)
Samsung's 3GAE process technology is the first process to use GAA transistor, which Samsung officially calls multi-bridge channel field effect transistor (MBCFET).
Samsung officially launched 3GAE and 3G 3GAP nodes about three years ago. Samsung said that the process will achieve 30% performance improvement, 50% power consumption reduction and up to 80% transistor density (including a mixture of logic and SRAM transistors). However, it remains to be seen how Samsung's performance and power consumption actually combine.
Theoretically, GAAFET has many advantages over the currently used FinFET. In a GAA transistor, the channel is horizontal and surrounded by the gate. The GAA channel is formed using epitaxy and selective material removal, which allows designers to accurately adjust the transistor channel by adjusting its width. Achieve high performance through wider channels and low power consumption through narrower channels. This accuracy greatly reduces the transistor leakage current (that is, reduces power consumption) and the variability of transistor performance (assuming everything is normal), which means faster product delivery time, time to market and higher output. In addition, according to a recent report by Applied Materials, GAAFET is expected to reduce the battery area by 20% to 30%.
Speaking of applications, its recently launched high vacuum system IMS (Integrated Material Solution) system for forming gate oxide stacks aims to solve the main challenges in the manufacture of GAA transistors, namely, the very thin space between channels and the necessity of depositing polysilicon. A gate oxide layer and a metal gate stack are formed around the channel in a short time. Applied Materials' new AMS tool can use atomic layer deposition (ALD), thermal step and plasma treatment step to deposit a gate oxide layer with a thickness of only 1.5 angstrom. The highly integrated machine also performs all necessary metering steps.
Samsung's 3GAE is an "early" 3nm manufacturing technology, which will be mainly used by Samsung LSI (Samsung's chip development department) and possibly one or two SF's other alpha customers. Please remember that Samsung's LSI and other early customers of SF tend to manufacture chips in large quantities, and it is expected that 3GAE technology will be widely used, provided that the output and performance of these products meet expectations.
Transitioning to a new transistor structure is usually risky because it involves new manufacturing processes and new tools. Other challenges are new layout methods, layout planning rules and routing rules introduced by all new nodes and solved by new electronic design automation (EDA) software. Finally, chip designers need to develop brand-new ip, which is expensive.
Foreign media: Samsung's 3nm yield is only 20%
According to foreign media Phonearena, Samsung foundry is the second largest independent foundry in the world after giant TSMC. In other words, in addition to manufacturing Exynos chips designed by Samsung itself, Samsung also manufactures chips according to the designs submitted by third-party companies such as Qualcomm, which represents factory customers.
Snapdragon 865 Application Processor (AP) is manufactured by TSMC using its 7 nm process node. On the 5nm Snapdragon 888 chipset, Qualcomm returned to Samsung and continued to rely on the Korean foundry to produce 4nm Snapdragon 8 Gen 1. This is the AP that currently powers high-end Android phones made by Samsung, Xiaomi and Motorola.
However, in February, it was reported that the yield of Samsung OEM on its 4nm process node was only 35%. This means that only 35% of chips cut from wafers can pass quality control. In contrast, TSMC achieved a yield of 70% when producing 4 nm Snapdragon 8 Gen 1 Plus. In other words, all things being equal, TSMC produced twice as many chips as Samsung did in the same period.
Therefore, TSMC finally received an order from Qualcomm to build its remaining Snapdragon 8 Gen 1 chipset and Snapdragon 8 Gen 1 Plus SoC. We also assume that TSMC will get the license to manufacture 3 nm Snapdragon 8 Gen 2, even if Qualcomm needs to pay a premium to TSMC to allow the exclusive manufacturer of this chipset to manufacture enough chips in a short time.
Although Samsung recently said that its output has been increasing, a report of Business Post said that the output of Samsung's 3nm process node is still far below the company's target. Although the full ring gate (GAA) transistor architecture of Samsung foundry introduced its 3 nm node for the first time, making it in the leading position in TSMC (TSMC will introduce its 2 nm node GAA architecture), the yield of early 3 nm production of Samsung foundry has been in the range of 10% to 20%.
This is not only the extremely low yield that Samsung needs to improve, but also the 35% yield experienced by Pisa rice in 4nm Snapdragon 8 Gen 1 is even worse.
Wccftech said that according to sources, the "performance version" of the first 3nm GAA chipset that Samsung will ship to customers from next year may actually be a new internal Exynos chip. It is reported that Samsung has been developing a new series of Exynos chips for its smartphones, but it is not clear at this stage whether they will be manufactured using 3 nm GAA process nodes.
TSMC and Samsung will soon have new challengers, because Intel has said that its goal is to take over the leading position in the industry by the end of 2024. It also took the lead in obtaining a more advanced extreme ultraviolet (EUV) mask aligner.
The second generation EUV machines are called high NA or high numerical aperture. The NA of the current EUV machine is 0.33, but the NA of the new machine is 0.55. The higher the NA, the higher the resolution of the circuit pattern etched on the wafer. This will help chip designers and foundries to create new chipsets, which contain even more transistors than the billions of transistors currently used in integrated circuits.
This will also prevent the foundry from passing the wafer through the EUV machine again to add extra functions to the chip. ASML said that the higher resolution pattern generated by the second generation EUV machine will provide higher resolution, which will reduce the chip features by 1.7 times and increase the chip density by 2.9 times.
By purchasing this machine first, Intel will be able to take a big step in regaining its leading position from TSMC and Samsung.
TSMC 3 nm production time exposure
According to the Taiwan media "United Daily News", TSMC and Samsung fought fiercely at 3 nm in the competition of the top three foundries, which always attracted the attention of the global semiconductor industry. According to the survey, due to the delay of development progress, Apple's next-generation processor still uses TSMC's 3 nm with 5 nm enhanced N4P this year, which has made a major breakthrough recently. TSMC decided to take the lead in adopting the second version of the 3-nanometer process N3B this year, and in August this year, it launched films simultaneously in the eighth phase of the R&D Center of Hsinchu 12 Factory and the P5 Factory of Conan 18 Factory, and formally adopted the FinFET structure to counter Samsung's GAA process.
According to TSMC, the company's 3 nm (N3) process technology will be another whole generation process after the 5 nm (N5) process technology. When N3 technology is introduced, it will be the most advanced technology in the industry, with the best PPA and transistor technology. Compared with N5 technology, the logic density of N3 technology will increase by about 70%, the speed will increase by 10- 15% at the same power consumption, or the power consumption will decrease by 25-30% at the same speed. The development process of N3 process technology is in line with expectations and makes good progress. In the future, it will provide a complete platform to support mobile communication and high-performance computing applications. It is expected that a batch of customer products will be received on 202 1. In addition, mass production is expected to begin in the second half of 2022.
As mentioned above, the fab 18 will be the main production plant of TSMC's 3 nm. According to the data, the Fab 18 in TSMC Conan is the focus of production expansion at present. There are four 5-nanometer and 4-nanometer factories in P 1p4 * * and four 3-nanometer factories in P5 P8 * *, while the Fab 18A in P 1 P3 is in mass production. As for Fab 65438+ in P4 P6,
While chip design companies are still "fighting for capacity", the field of wafer manufacturing is another scene. For wafer manufacturers, what is more important now is the breakthrough of 3nm. Whoever takes the lead in mass production of 3nm will occupy the commanding heights of the future wafer manufacturing industry and even affect the product roadmap of chip giants such as AMD and NVIDIA.
There is no doubt that at the node of 3nm, only TSMC and Samsung can compete at present, but Intel is obviously also making efforts in advanced manufacturing technology. However, judging from the recent news, TSMC and Samsung are quite bumpy in 3nm mass production. Gartner analyst Samuel Wang said that the 3 nm slope will take longer than the previous nodes.
Recently, a report citing semiconductor industry sources shows that TSMC is reported to have difficulties in the production of 3 nm process. The key rumor reported by the source is that TSMC finds it difficult to achieve satisfactory yield in its 3 nm FinFET process. But so far, TSMC has not publicly acknowledged any delay of N3. On the contrary, it claims that it is "making good progress".
As we all know, TSMC 3nm adopts FinFET structure on the transistor. FinFET adopts three-dimensional structure, which increases the contact area of the circuit gate, thus making the circuit more stable and realizing the goal of continuous miniaturization of semiconductor manufacturing process. In fact, the FinFET transistor walking at 3nm is more or less the limit, and then it will encounter physical limit problems such as current control leakage caused by process miniaturization, but TSMC still chooses it, largely because it can have a superior cost structure without changing too many production tools. Especially for customers, the production cost can be reduced without too many design changes, which can be said to be a win-win situation.
According to the previously published data, compared with the 5nm chip, the logic density of TSMC's 3nm chip will increase by 75%, the efficiency will increase by 15%, and the power consumption will decrease by 30%. It is reported that TSMC's 3nm process started risk trial production in March, 20021,and was delivered in small batches. It is expected that commercial production will begin in the second half of 2022.
From the factory point of view, Phase 4-6 of Conan 18 Factory in Taiwan Province, China is TSMC's 3nm mass production base. As for customers, as can be seen from the above, Intel, Apple and Qualcomm all chose TSMC. Chen Chali, an analyst at Morgan Stanley, recently published a report saying that TSMC is almost in a monopoly position in the 3-nanometer chip foundry market in 2023, and its market share is close to 100%.
Different from TSMC's problem of yield, Samsung's difficulty in 3nm lies in the backward number of patents IP for 3 nm GAA process. According to South Korean media reports, Samsung is uneasy about the lack of patents related to the 3 nm GAA process.
Samsung has adopted a full gate (GAA) transistor architecture for transistors. Compared with the FinFET transistor of TSMC, the 3nm process cost based on GAA is definitely higher, but from the performance point of view, the transistor based on GAA architecture can provide better electrostatic characteristics than FinFET and meet certain gate width requirements. It can be seen that the chip size can be made smaller by using GAA structure under the same process.
Planar transistor, FinFET and GAA FET.
Compared with the 5nm manufacturing process, Samsung's 3nm GAA technology improves the logical area efficiency by more than 35%, reduces the power consumption by 50%, and improves the performance by about 30%. In June last year, Samsung officially announced that the 3nm process technology had successfully flown. In addition, Samsung also announced that it will launch an early version of 3nm GAA in 2022, and its "performance version" will be shipped in 2023.
At present, in terms of factories, it is reported that Samsung may invest 654.38+0.7 billion dollars in the United States to build a 3nm chip production line. On the customer side, Samsung didn't specifically disclose it, but it is reported that Qualcomm, AMD and other TSMC heavyweight customers are interested in introducing Samsung's 3-nanometer process. However, due to the Korean media reports mentioned above, Qualcomm has handed over the OEM order of its 3nm AP processor to TSMC, and Samsung's 3nm customer remains a mystery.
After Pat Gelsinger became the CEO of Intel last year, the IDM giant, who had tried water in OEM field, returned to this market. At the same time, they also put forward great ambitions.
At this month's 18 investor meeting, Intel CEO Pat Gelsinger once again stressed that Intel's 2nm process will be mass-produced in the first half of 2024, earlier than TSMC, which means that the competition between wafer foundry business and TSMC will be more intense two years later.
Although Intel did not disclose the 3nm process too much, Digitimes' research report last year analyzed the transistor densities of TSMC, Samsung, Intel and IBM at the same named semiconductor process nodes, and compared the transistor densities of each company at 10nm, 7nm, 5nm, 3nm and 2nm.
In terms of factories, Intel stressed that it will invest 80 billion euros to build factories in Europe. Christin Eisenschmid, head of Intel Germany, revealed in an interview that 2nm or smaller chips will be produced in Europe. Intel regards 2nm as an important key to expand production capacity in Europe, so as to avoid falling behind in the future advanced technology competition.
Generally speaking, on the 3nm node, TSMC, Samsung and Intel who will be the final winner may only be judged by time, but from the current situation, TSMC may be slightly better.
3nm has reached the physical limit of Moore's Law. How should the future develop? This has become an urgent problem for researchers all over the world. At present, researchers mostly try to find solutions in transistor technology and materials.
The above-mentioned GAA transistor used by Samsung in the 3nm process is a good choice after 3nm. GAA designs a gate around the channel, which can reduce the leakage voltage and improve the control of the channel, which is the key to reduce the process nodes. It is reported that TSMC will also use GaAs transistors in the 2 nm process.
Nanowires are nanostructures with diameters in the order of nanometers. One of the basic attractions of nanowire technology is that they exhibit powerful electrical properties, including high electron mobility due to their effective one-dimensional structure.
Recently, researchers from HZDR announced that they have proved the long-term theoretical prediction of nanowires under tension through experiments. In the experiment, the researchers made nanowires composed of GaAs core and indium aluminum arsenide shell. Finally, the results show that researchers can indeed improve the electron mobility of nanowires by applying tensile strain to them. It is measured that the relative mobility of unstrained nanowires and bulk GaAs increases by about 30%. Researchers believe that they can achieve a more significant increase in materials with large lattice mismatch.
Recently, an Intel patent on "stacked interdigital transistors" has attracted people's attention.
Intel said that the new transistor design can eventually realize 3D and vertically stacked CMOS architecture, which allows to increase the number of transistors compared with the most advanced tri-gate transistors. In the patent, Intel describes the use of nanoribbon transistors and germanium thin films, which will act as dielectric barriers and repeat in each vertically stacked transistor layer, ultimately depending on the number of transistors stacked on each other.
It is understood that Intel is not the first company to cite this manufacturing method. The Belgian research group Imec proposed this method in 20 19. According to the simulation results of the first standard cell of Imec, when applied to 2nm process nodes, this technology can significantly improve the transistor density compared with the traditional nano-chip method.
Vertical Transmission Field Effect Transistor (VTFET) was jointly announced by IBM * * *(Samsung * * *, aiming to replace FinFET technology used in some of the most advanced chips at present. The new technology will stack transistors vertically, allowing current to flow up and down in the transistor stack, instead of laying transistors flat on the silicon surface and then the current flows from one side to the other, which is the method used on most chips at present.
According to IBM and Samsung, this design has two advantages. First, it will allow many performance limitations to be bypassed and extend Moore's Law beyond the threshold of 1 nm. At the same time, it can also affect the contact point between them to improve the current and save energy. They said that the design may double the performance or reduce the energy consumption by 85%.
In fact, transistor manufacturing is only a part of solving the evolution of advanced technology after 3nm, and chip design is also very important. The impact of on-chip interconnection, assembly and packaging on device and system performance must be minimized.
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