The CEC (Consumer Electronics Control) channel is optional. Through CEC channel, some advanced control functions between audio and video devices can be realized, such as supporting two-way communication between video source and digital TV, realizing simultaneous power-on, automatic power-on, automatic signal routing, remote control and other functions.
Figure 1 HDMI system structure diagram
Electronic EDID data structure
E-EDID is a data structure defined by VESA, which is an optimized display format data specification for PC monitors. It is stored in the EEPROM memory dedicated for the monitor, and the data structure is 128 bytes. The PC host and monitor access the data in the memory through DDC channel to determine the display properties of the monitor, such as resolution, aspect ratio and other information. HDMI adopts this data structure. In the HDMI specification, the same example uses DDC channel to access the EDID memory to determine the functions and attributes of the display device.
According to the HDMI specification, the first 128 byte of EDID must be a data structure conforming to EDID 1.3, and the second 128 byte must be a CEA EDID time series extension data structure conforming to EIA/CEA-861b.
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HDMI (high-definition multimedia interface) is mainly used to transmit high-definition audio and video signals.
HDMI pin:
HDMI has five pin types: A, B, C, D and E, and the most common pin type on the market at present is Type A:
In ...
Transmission process:
HDMI TMDS transmits three kinds of data (including Hsync and Vsync, totally four kinds):
HDMI data transmission has three channels: TMDS0, TMDS 1 and TMDS2, and the transmission flow of each channel is the same:
If 8-bit data enters the TMDS encoder, a 10-bit TMDS signal with strong anti-interference is obtained, and then serialized and output; After receiving the serial HDMI signal, the receiver recovers the signal to obtain the TMDS signal with 10 bit, and finally the original 8-bit data is decoded by the TMDS decoder.
The whole transmission process is as follows:
If video data is transmitted in RGB format, all 24-bit inputs of three channels will be occupied, of which channel 0[7:0] is used for transmitting B, channel 1[7:0] is used for transmitting G, and channel 2[7:0] is used for transmitting R. ..
If the data island is transmitted, it takes up three channels * * * 10 bit input, channel 0[3:2] is used to transmit the data island header, and channels 1[0:3] and 2[0:3] are used to transmit the data island content.
If the preamble is sent, it will occupy two channels of 1, 2 * * 4-bit input. Channel 1[ 1:0] and channel 2[ 1:0] are CTL 0, CTL 1, CTL 2 and CTL 3 respectively, which are used to judge the next step.
For Hsync and Vsync, it will occupy two bit inputs of channel 0, channel 0[0] is Hsync and channel 0[ 1] is VSync.
Transmission period:
The TMDS data transmission of HDMI can be divided into three transmission periods:
Hsync and Vsync are transmitted in the control cycle, and the preamble is transmitted in the last stage of the cycle.
During the data island, data islands (packets) will be transmitted, and there will also be Hsync and Vsync.
Video data (video pixel data) is transmitted during a video data period.
The total period of a frame is as follows:
The conversion of three transmission cycles is as follows:
On the left is the control cycle, which transmits Hsync, Vsync and preamble.
In the middle is the data island period, which transmits Hsync and Vsync, as well as two packet headers and packets (one packet every 32 clocks); In addition, both ends of the data island will use guard bands to protect and isolate the data of the data island, because most of the data transmitted at this stage is very important, such as the resolution of the image, which determines the display mode of the video data in the later stage.
On the right is the video data island, which transmits video pixel data. At the beginning of this period, there was a guard band.
Data island packet structure
All data island packets have a period of 32 clock pulses, that is, one packet is sent every 32 clock pulses.
Taking the above picture as an example,
The header is BCH block 4, which is transmitted by channel 0[2]. 32clk means there are 32 bits, which means 44 bytes. The first three bytes are the header and the last byte is the check code.
The data packet is BCH block 0, 1, 2, 3, which are transmitted by 8 lines of channel 1 and channel 2 * * * respectively, and the check code of * * * is 24 bytes and 6 bytes.
Parity code is used to check whether there are errors in the transmission of HDMI cable. If the packet is checked for errors at the HDMI receiver, if there is only one bit error, it can be corrected, and the error exceeding 1 bit will be judged as invalid packet (because HDMI has been sending data, it is impossible to resend the error packet? )
Therefore, at the receiving end, the parity bit of each BCH block needs to be taken out for calibration after unpacking.
There are various types of data packets, please refer to the HDMI specification for details.
Audio clock
The sampling rate of audio is 44 100, 48000, 192000, etc. It's varied. In HDMI transmission, audio is PCM-level (uncompressed) transmission, and PCM data is scattered in each packet. In order to get the data of each audio frame, we also need to know the sampling rate of audio. HDMI specifies the transmission mode of audio:
The reconstruction of audio sampling rate fs depends on the following main parameters:
TMDS clock
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ordinary
On the transmitting device side, the known parameters include sampling rate fs, video clock (TMDS clock) and preset parameter n, and CTS:
CTS=N？ fTMDS 128×fx
On the receiving device side, TMDS clock can be obtained through hardware devices, and N is transmitted with CTS through audio packets, and fs:
128? fs=N×fTMDSCTS
In order to maintain the stability and accuracy of the receiver fs, it is necessary to carry out phase locking, that is, use VCO (Voltage Controlled Oscillator) to generate an appropriate frequency, and then use PFD (Frequency and Phase Detector) to lock the frequency.
1. First of all, because VCO has an optimal working area, such as (200MHz~500MHz), in order to ensure that VCO is at the optimal working frequency, we can push it back from behind and multiply the output fa 128 first.
fvco=fa 128×S×S2
Because there are only a few fa 128 (44. 1k, 48k, etc. ), S and S2 can be easily obtained.
2. Then, for faster frequency matching, it is necessary to divide the nearest frequency fx (that is, crystal oscillator clock fcrystal) or fv (pixel clock), and also divide the frequency fvco to make the two trends equal. For subtle differences, you can use D code to correct them.
fvcoM=fxK
3. Finally, do PFD phase locking.
4. The feedback operations in steps 2 and 3 are carried out circularly, and finally a relatively stable fvco can be obtained.
Finally get
fa 128=fvcoS×S2
hot swap
HotPlug is hot plug. When the interface is connected, it can be judged whether the device exists for subsequent work.
The HDMI source device will monitor the hot plug port of the receiving device. If the Hotplug is high, prove that the device can work, and then read the DCC. If it is low, it proves that the device is disconnected.
HDMI stipulates that when the 5v pin of HDMI is powered off, it is necessary to read DCC, that is, it is necessary to ensure that the Hotplug is high.
Hot plug connection:
It is powered by a 5v pin. When the 5V power supply is disconnected, 5V voltage will be injected into HDMI HPD and hot plug. At this time, HPD detects 5V voltage (high), so you can come and read the EDID. However, this method has a disadvantage. 5V voltage will affect hot plug. Once the hot plug pin can't withstand the charging of 5V, it will be punctured, so HPD can only detect low.
Additional GPIO pins and transistors are used to control whether HDMI HPD is 0 or 1. If HDMI0_HPD_CTL outputs 0, the transistor is turned off and HDMI0_HPD detects a high level. If HDMI0_HPD_CTL outputs 1, the transistor is turned on and HDMI0_HPD detects a low level.
HDMI receiver
For example, if the TV is the receiving end of HDMI, then the receiving end of HDMI needs to do something.
HDMI can receive TMDS data through three channels, namely TMDS clock, hot plug and I2C pin for DCC transmission. I have talked about TMDS data and setting up hot plug, and then I will analyze TMDS clock.
TMDS clock is a pixel clock, that is, the clock frequency used by a pixel. The TMDS clock is transmitted to the receiving end through the clk pin, but the receiving end doesn't know the frequency of the TMDS clock sent by the sending end, so it needs to pass the Phy(HDMI hardware frequency setting part? ) for phase locking. However, due to the wide bandwidth of HDMI (480P@60Hz is 25.2MHz, 1080P@60Hz is 162MHz, or even as high as 340MHz), the general VCO (voltage controlled oscillator, frequency generated by voltage control) cannot cover such a large range, so it is necessary to set the Phy:
Firstly, the input frequency is detected in which frequency band, and then different settings are made according to different frequency bands.
Use the crystal oscillator generated by TV to count, and you will know the TDMS clock.
fcrystal=count×fTMDS
Or use 1024 TMDS clock to calculate the number of crystal oscillators.
1024×ft MDS = counting× f crystals
Since the video signal is changed from RGB 8 bits to 10 bits after TMDS coding, and then serialized, the clock actually used to receive TMDS data should be:
fReceiveClock= 10×fTMDS
In addition, ReceiveClock can be obtained by using TMDSClock as a reference and hardware phase locking, instead of directly using the above multiplication.
After receiving the received clock, you can set the frequency of PLL, and then sample three channels to obtain TMDS data.
Timing detection
The receiver still needs timing detection, because if the device can support (such as chroma), HDMI can freely replace the timing, and when the timing is replaced, the receiver needs to reset the Phy. Therefore, it is necessary to detect whether the timing is replaced by detecting the change of frequency. There is usually an interrupt service (or loop) thread to detect the change of frequency. Once the frequency is changed, the process will inform to reset the Phy to ensure the correct operation of HDMI.
HDCP for HDMI copyright content protection
HDCP transmission through DDC
HDCP is mainly used to protect copyrighted videos. For example, if a Blu-ray DVD player can play a Blu-ray DVD, and the DVD has been authorized by HDCP, and now you want to export DVD images to a TV, but the TV has not been authorized by HDCP, the TV may not be able to play the images, or the playback quality may be degraded. For example, if there is snow, the image will change from 1080p to 480p, or there will be no sound.
HDCP authenticates through the interaction between two devices, and the authentication process is as follows.
1. the transmitter will send a key An(64 bits) and Aksv (40 bits of key selection vector) to the receiver.
2. After receiving An, the receiver will also send a Bkvs and a repeater (indicating whether device B is a repeater device) to the transmitter.
3. The transmitter starts the HDCP authentication code algorithm:
In order to understand the algorithm, we first need to know what ksv is used for.
Inside each HDMI device, 40 sets of 64-bit keys, key[40], will be saved.
Kvs has 40 bits, and each bit is an index. When a certain bit n of kvs is 1, the key [n] will be taken out.
Add all the bonds [n] to get km,
4. The receiver can also do the HDCP authentication code algorithm, and this step gets kilometers. '
5. Both transmitter and receiver will use km\km' to execute hdcpBlkCipher and get the values of R0 and R0'.
6. After100 ms, the receiver sends R0' to the transmitter for comparison, and if they are equal, the authentication is considered complete. Of course, km = km' can guarantee R0 = R0'.
7. After that, the sender and receiver will run hdcpBlockCipher once per frame, but the parameters are the last generated ks and M, and the generated new parameters are Ks, M and T..
8. In frame 128, another r = t.
9. After the first communication interval of 2 seconds, authenticate again.
10. Subsequent steps 7, 8 and 9 are used for iterative authentication.
In addition, HDMI supports faster and more frequent authentication methods from 1. 1.
It is the lower half of the communication diagram of upper-level equipment.
1. In each multiple frame of 16, XOR T is performed with the 0 pixel of channel 0 of the current frame to obtain Pj.
2. After the 0 pixel of channel 0 arrives at the receiving end, it is also XOR with the t' of the receiving end to get p' j..
3. The receiver sends P'j to the sender, compares it with Pj, and if it is the same, it is authenticated.
Understanding HDCP is very helpful to deal with HDMI anomalies. For example, snowflakes appear from time to time, which may be due to poor signal, resulting in 0 pixel error of Channel0, so the second-stage authentication may sometimes be unsuccessful. ...
General process of HDMI receiver
HDCP
HDCP is a high-bandwidth digital content protection, and TMDS signals should be encrypted by HDCP to ensure that digital signals cannot be easily copied.
8b/ 10b
8b/ 10b is a digital processing method, which was first patented by IBM. Now its patent has passed the protection period and has become a public technology. Its purpose is to improve the anti-electromagnetic interference (EMI) ability of digital signals and improve the accuracy of signals. To put it simply, the working mode is to re-encode the digital signal consisting of eight zeros and 65438+ zeros, with the first five being reorganized into six and the last three being reorganized into four. After this conversion, digital signals in groups of eight are converted into a group of 10. After the transmission is completed, the receiver decompiles and recovers the digital signal.