Sorry, it seems that AMD is really determined to protect jiaozi to the end.
"It remains to be seen whether this seemingly large I/O processor will really be put into production by global foundries. The probability should be high. 」
Old love is always the most beautiful, and AMD has indeed chosen a proven and mature process.
On the second day after the author submitted a seriously worded comment, Anandtech interviewed Mark Papermaster, the chief technical officer of AMD, and directly hit the author in the face ... Er, he gave a positive answer to both questions. For the subjects who have experienced the glory of AMD K8 and Intel Pentium 4, the current mood will be more or less complicated.
AMD disclosed for the first time at the microprocessor forum in 20001year1October that K8 will integrate dual-channel DDR memory controller, which will change the familiar multiprocessor environment from SMP with the same physical memory to decentralized CC-NUMA(ACPI specification has also added corresponding extended specifications, such as static resource affinity table, storing the topology information of multiprocessor, And the sharp "hint" that there was a native dual-core K8 plan from the beginning later turned into a satirical book, in which AMD publicly mocked Intel for playing "double stuffing jiaozi" in the late Pentium4 and Merom era.
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In those years when K8 family products came out one after another, not only AMD's K8, but also IBM's Power5 relied on integrated memory controllers, which made the overall performance overwhelming, making all the high-end RISC processors at that time, including Intel's flagship An Teng 2, flat to the point where even mom could not recognize them.
In short, the advantages and disadvantages of the integrated memory controller are also obvious:
Advantages:
Efficiency: "The closer, the faster." When multi-core CPU becomes the mainstream, you can't continue to let hungry processors grab the external system bus card and the same physical memory, can you? Cost: Thanks to Moore's Law, this is not a law, it is the responsibility of all chip manufacturers in the world. The higher the chip integration, the lower the overall cost of manufacturing a computer in theory. Disadvantages:
Technology: It is not a simple matter to combine the functions of traditional Northbridge with CPU in the same process, let alone build a high-quality and high-compatibility memory controller. It is rumored that AMD suffered a lot in developing K8, and Intel heard that it also paid a lot of tuition fees on the way to Nehalem. Elasticity: If we want to support the new memory specification, we have to design a new processor and change pins. If we consider the related mechanisms (such as Chipkill) to enhance the reliability of memory data, it will be more complicated and tricky. After 17 years, AMD made a major strategic turn on Zen2, which was "cutting sausage" at worst and "pragmatic" at best.
Reference article:
Hard technology: What CPU and GPU surgeons should know more about AMD 7nm technology?
In fact, the photo of the "Nine Stuffed jiaozi" EPYC sample shown by AMD CEO lisa su in "The Next Horizon" is enough to detect the difference: the grain area of a 7nm process eight nuclear CPU chiplet is estimated to be only 60-70mm? , significantly more than 83.27mm? Apple A 12 is smaller, but the 14nm process Zeppelin, which includes dual-channel DDR 4 memory controller, a large number of I/O interfaces and auxiliary security processors, is 2 13mm? No matter how you look at it, there is definitely more than I/O (server hub I/O Mux in the picture) in the functional units moved out of the original chiplet in eight nuclear. Otherwise, how can the I/O processor produced by the global foundry 14nm process be so fat that it looks bigger than the sum of eight small chips?
It is reasonable to configure EPYC (Socket SP3) 8-channel DDR 4 memory. After all, it is unlikely that 8 CPU chiplets will have 1 group memory controllers, and the cache consistency protocols of Infinity Fabric and MDOEFSI are not omnipotent, so the running efficiency of the whole memory subsystem is a big question mark. What's more, does the Ruilong of Socket AM4 have to install two small chips to force the 16 core configuration of dual-channel DDR 4? (But many DIY players should really want to see this scene. )
In a word, the huge I/O processor of the new EPYC must have an 8-channel DDR 4 memory controller in addition to USB SATA PCIe, and it will have an 87% chance of being named as a system controller chip.
As for the real protagonist, the 7nm CPU, according to the existing data, only CCX and Infinity Fabric are kept in the 7nm process chiplet, and then two quad-core CCX (*** with 8MB L3 cache) are combined into one, and the total capacity of eight nuclear CCX*** is doubled to a single 32MB L3 cache. As a result, the 1 64 core EPYC has a huge L3 cache of up to 256MB, which is 6.6 times that of Intel's current 28-core Xeon SP 38.5MB (the above is purely the author's personal guess. Please don't blame me if you accidentally hit it. Please don't scold me if you haven't guessed. )
It is worth noting that in the past, from Pentium Pro (CPU+L2 cache) all the way to the scary IBM Power5 (four CPUs+four L3 caches), multi-chip packaging was very expensive, which is also the main reason why it is rare in general consumer products, but the wind direction in the real world seems to have changed.
If AMD keeps the product route of "single chip stacking" to save R&D expenses and bet on the yield and cost of multi-chip packaging in the future, what interesting developments will there be in the future?
AMD continues the strategy of "winning by quantity", and its primary goal is the cloud data center. The progress of DDR5 may be faster than the average computer player expected, and AMD wants to strive for more flexibility. AMD will definitely develop a smaller and cheaper I/O processor for Socket AM4 with dual memory channels. Socket AM4 Ruilong will have a 16 core product with two chiplets and a small I/O processor. Look at the lesson of Intel Kaby Lake-G, whether AMD will be possessed or not, even APU will do it, and you can wait and see. Finally, the author ends this comment with a friend who pays attention to AMD, a patent related to I/O processors:
"Seriously, I think Intel is really in big trouble. 」