Manufacturing method of power MOS field effect transistor with groove source structure
The application number is cn201310314819.0, and the application date is 20 13.07.25.
Publication (announcement)No. CN10424133a Publication (announcement) date 20 14. 12.24.
At present, the validity of legal status is under review.
Classification number h 01l 21/336 (2006.438+0) i; h 0 1l 2 1/28(2006.0 1)I
Applicant (patent right) Yu Guoqing
Address: Room 2003, Building 5 15 126, Suzhou Industrial Park, Jiangsu Province
Inventor (designer) Yu Guoqing; Wu Yongjun
Priority 2012.07.27cn201210262341.7
Patent agent
abstract
The invention relates to a manufacturing method of a power MOS field effect transistor with a groove source structure. The manufacturing processes of photolithography, etching and depositing a metal layer are sequentially adopted on the source contact area in a single unit array, and the etching of the source contact area in the single unit array adopts the same photolithography pattern as a mask, and is carried out by combining dry etching and wet etching, so that the source metal layer simultaneously contacts a horizontal contact platform at the top of a source region and a longitudinal contact side surface at the side of the source region. According to the manufacturing method of the power MOS field effect transistor, the contact area between the source metal layer and the source region is increased, so that the contact resistance of the source metal is reduced, the energy loss is reduced, and the device performance is improved.