From graphics chips to x86 processors, AMD has been playing with MCM in recent years. Even in Zen 2 generation, even the "processor core (CCD)" and "Northbridge memory I/O controller (IoD)" were divided and ruled, and it is expected that X3D with "2.5D" and "3D" package stacks will be introduced in the future. This advanced packaging technology has long been the battlefield of semiconductor industry.
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Why do you need multi-chip packaging? Wouldn't it be easiest to make all the functions into the same 1 chip? However, there are no semiconductor processes in the world that can meet "all functions", such as digital logic, I/O, various memories, analog/radio frequency, etc. And their characteristics are very different, so they reluctantly "sent to a pile." Either things can't be made, or product yield is sacrificed, or some functions are difficult to optimize. AMD will divide Zen 2 into several particles with different functions, which is not unreasonable.
Therefore, starting from 1990, multi-chip packaging products are very common in the market, including high-performance processors that are familiar to all disciplines. By "divide and rule", IP with different functions is located at the most suitable process node.
Like Intel Pentium Pro ending in 1995, will it be 0.50? The P6 processor core in MobiCMOS technology is encapsulated with 256kB L2 cache.
At the same time, NexGen (later acquired by AMD) Nx586-PF will also be 0.44? The Nx586 of M process and the Nx587 auxiliary floating-point operator of the same process are packaged in the same 1 package.
In the high-end server market in 2004, the invincible IBM Power5 concentrated four dual-core Power5 processors and four 36MB L3 caches into an 8-core huge module.
As for Intel and AMD, there is no need to waste space on a long list of "double stuffing jiaozi" from 2005 to now, and all subjects understand it.
2.5D packaging that breaks through the limitation of SiP: Take the 2.5D packaging technology of CowOS (Chip on Chip) of TSMC as an example. Compared with the traditional "2D" SiP, the main difference is that the 2.5D package is located between the SIP substrate and the chip. Inserting a silicon interlayer and connecting the upper and lower metal layers by through-silicon vias overcomes the problem of difficult wiring of SiP substrates (such as multilayer printed circuit boards) at high density, thus limiting the number of chips.
A large number of high-end products using HBM memory, From AMD Vega20, NVIDIA A/KOOC-0/00/P/KOOC-0/00/V/KOOC-0/00, Google's second/third generation TPU, Xilinx's high-end FPGA, Intel's NNP-T/KOOC-0/000 (Spring Crest, The artificial intelligence training processor, Habana Gaudi, Intel's new favorite of artificial intelligence, SDN (Software Defined Network) switching chip.
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As for TSMC's "3D" package InFO (Integrated Fan-out), it can reduce the package thickness by 30%, and even after defeating Samsung to grab the A 10 processor of iPhone 7 (unfortunately, the author bought the iPhone 6s with Samsung A9 processor), it has always been the key to eating Apple orders.
Intel camp: 2.5D Emib and 3D Foveros TSMC has 2.5D CoWos and 3D InFO, then Intel certainly has 2.5D EMIB (Embedded Multi-die Interconnect Bridge) and 3D Foveros.
The key technology of EMIB lies in the "silicon bridge" buried in the package substrate for connecting the die. Its representative products are Kaby Lake-G which "binds" Intel Kaby Lake processor core, AMD Vega 20/24 graphics core and 4GB HBM memory, and its own Stratix X FPGA.
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Foveros is a real 3D "layered music", including Lakefield of Intel stacks 10 nm process (P 1274), I/O chip of 22nm process (P 1222) and POP (1 Big Four Small Core).
EMIB+Foveros = Co-EMIB Intel announced co-emib on July 20 19. To put it bluntly, it is great to connect multiple Foveros packages with EMIB and continue to stack the bedstead into a single chip that integrates more functions.
Odimib and Foveros, which extend the concept of EMIB, are not without their shortcomings. In particular, although the latter can enjoy the amazing bandwidth between chips (after all, they are all stacked face to face), how to supply power to the "top layer" is a great challenge. Via silicon (TSV) will increase the resistance, while increasing the number of TSV will decrease the resistance, but it will increase the chip area (Intel estimates that it is between 20-70%).
In addition, "folding music" also means that heat dissipation is difficult, because the chip pressed on it will hinder the path of heat flow conduction. This is also the main reason for the coexistence of 2.5D and 3D. For example, TSMC's InFO actually paid the price of "sacrificing some performance" and may not be suitable for high-performance products.
Conversely, flattening all chips on the same silicon interlayer with EMIB can avoid the problems of silicon perforation and heat dissipation, but it loses all the advantages of 3D packaging. A larger silicon interlayer means higher cost.
As an extension of the concept of EMIB, ODI (Omni-Directional Interconnect) was born for this purpose. It can be used in both 2.5D and 3D packages, and it can achieve the performance that EMIB can't achieve (data transmission capacity per square millimeter 1TB/s, heat per data transmission bit of 0. 1pJ) with lower cost and easier heat dissipation. Unlike EMIB, which can only be bridged horizontally, ODI has the function of "up, down, left and right", which fills the gap between EMIB and Foveros and provides better flexibility for the connection between many small chips in the package.
Through ODI, the "top" chip can be horizontally interconnected with other chiplets, similar to EMIB, but the bottom chip can also be connected through silicon vias, similar to Foveros. The vertical vias of ODI are much larger than the traditional silicon vias, which can reduce the resistance, release more area with fewer silicon vias, reduce the chip size, and obtain higher bandwidth, lower delay and stronger power transmission.
There are two main types of ODI applications, and each type has two options (copper columns or cavities for packaging substrates).
The first one is to connect the top chip (ODI 1), which avoids the close stacking of two chips, which is beneficial to heat dissipation and has the advantage of high bandwidth of Foveros, and does not need a silicon adapter board like EMIB.
At first glance, it seems to be no different from EMIB, but the following example of connecting the processor directly to the memory for efficient operation should make you feel more, and then you can guess where ODI is hidden.
If you can't turn your head, imagine ODI Type 1 as an overpass in the middle of the Petronas Towers in Kuala Lumpur, Malaysia, or try to make up for the author's "doing a cordless bungee jump" from above.
The second application (Type 2) puts ODI completely under the chip to connect other functional units, such as I/O, memory or auxiliary processor (please use your imagination to make up for this missing link).
These two application architectures can also be mixed and matched to realize more flexible multi-chip packaging.
Next generation AIB:MDIO has long been concerned about Intel process and packaging science. When you see MDIO (Multi-Chip I/O), you may be confused for a moment and just scratch your head like the mayor.
In fact, in 20 17, Intel tried to use EMIB as a "silicon bridge" to connect the die, named it "AIB (Advanced Interface Bus)", and publicly licensed it for free to "build an industrial ecosystem". Intel also donated AIB to the Defense Advanced Research Projects Agency (DARPA) in 20 18 as a patent-free interconnection standard for small chips.
MDIO is the next generation AIB, which provides a standardized SiP physical layer interface for EMIB and can interconnect multiple chiplets. The data transmission rate of pin is increased from 2Gbps to 5.4Gbps, and the IO voltage is reduced from 0.9V to 0.5V V. The so-called "bandwidth density" is even better than that of LIPINCON of TSMC. But we also know that no matter how good the technical specifications on paper are, whether it is convenient for customers to import them into actual product design is another matter. These details can hide the mystery of the wafer foundry industry.
Of course, the Bao jiaozi Competition is in the ascendant, and Intel has repeatedly demonstrated the concept samples of these advanced packaging technologies in past public activities. Perhaps we will soon see Intel and AMD competing in various "fancy jiaozi competitions".
The long list of gobbledygook with words and the garbled code produced by the collapse of the human brain above will be more exciting if the subjects add a previous briefing. I heard that the number of words accumulated in this article has exceeded twice the standard of engadget column.
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But every time I think of the 18-inch wafer factory and related production equipment that still doesn't exist on the earth, I recall the 18-inch wafer samples I visited at Intel headquarters, and then I look at the 14nm process capacity crisis and the 10nm process yield problem that Intel has not solved for two years, and then I think about how this company did it more than ten years ago. Leading the technological trend of the whole semiconductor industry ",I don't criticize Intel severely for" why not take the lead to rescue the production capacity of 18 inch wafers ". I'm really sorry for myself who used to sit under the IDF keynote. All subjects should understand the author's painstaking efforts.
Then when it comes to AMD's X3D, it's almost time to talk about the rumored EHP (ExScale Heterogeneous Processor) project. It is said that two mysterious patent rights have revealed many interesting clues, but let's wait until the author has had enough fun, Keke.
Tracing the Hardware World, Archaeological Exploration, Wangying Technology