Patent name: Method for making a circuit structure that improves the linearity and power-added efficiency of a power amplifier
Technical field The present invention relates to a circuit structure that improves the linearity and power-added efficiency of a power amplifier .
Background Art Power amplifier is a key component in wireless communication systems, and its linearity and efficiency have always been the focus of attention. With the development of third-generation mobile communication systems (such as WCDMA, CDMA2000), linear modulation technology is increasingly widely used. The linearity of the power amplifier plays a crucial role in whether the communication system can transmit the amplified data signal without distortion. The better the linearity of the power amplifier, the less likely the signal waveform amplified by the amplifier will be distorted, so that the input data signal can be ideally amplified and output. In addition, the efficiency of the power amplifier is also another focus of research. The energy consumption of the power amplifier accounts for about 1/3 of the energy consumption of the wireless communication transmission system it consists of. Improving its efficiency plays an important role in improving the efficiency of the entire transmission system. For high-power wireless communication transmission systems such as base stations and radars, improving efficiency can reduce the power lost and improve the energy utilization of the transmission system; while for mobile phone and other transmission systems powered by batteries or accumulators, it can improve Efficiency allows these devices to work longer. Considering the importance of efficiency and linearity to power amplifiers, currently, how to make power amplifiers have higher efficiency while meeting high linearity requirements has become the focus of research. At present, the main methods to improve the linearity of power amplifiers include feedforward technology, feedback technology, and envelope elimination and restoration technology. Although feedforward and feedback technologies can effectively improve the linearity of the power amplifier, they will greatly reduce the power added efficiency (PAE) of the power amplifier. Although envelope elimination and restoration technology can improve the linearity of the power amplifier without affecting the efficiency of the power amplifier, the circuit structure used in this technology is very complex, does not utilize the circuit design, and increases the cost of circuit manufacturing.
Content of the Invention
The purpose of the present invention is to provide a circuit structure that improves the linearity and power-added efficiency of a power amplifier, so that without increasing the static power consumption of the power amplifier, It not only enhances the harmonic suppression of the power amplifier, but also significantly improves the linearity and power-added efficiency of the power amplifier. The technical solution of the present invention is a circuit structure that improves the linearity and power-added efficiency of a power amplifier. The power amplifier is provided with an input transistor and an output transistor, which are stacked together to form a Cascode structure. The collector of the output transistor and A second harmonic series resonance network that suppresses the output of the second harmonic signal is connected between the ground, and a third harmonic parallel connection that reflects the third harmonic signal back to the collector is connected between the collector of the output transistor and the output matching network. Resonant network. The resonant network is used to control harmonic signals, thereby suppressing harmonic signal output and improving the linearity and power-added efficiency of the power amplifier. Further, in the above-mentioned circuit structure for improving the linearity and power-added efficiency of the power amplifier, the second harmonic series resonance network includes a fourth capacitor and a second capacitor connected in series between the collector of the output transistor and ground. Inductor; that is, the input end of the second harmonic series resonant network is connected to the collector of the output transistor and the output end is connected to ground. It short-circuits the second harmonic signal output by the collector to ground. Further, in the above-mentioned circuit structure for improving the linearity and power-added efficiency of the power amplifier, the third harmonic parallel resonance network includes a third harmonic connected in parallel before the collector of the output transistor and the output matching network of the output port of the power amplifier. Five capacitors and the third inductor; that is, the input end of the third harmonic parallel resonance network is connected to the collector of the output transistor, and the output end is connected to the output matching network of the power amplifier circuit. It opens the third harmonic signal output by the collector and converts the third harmonic The signal is reflected back to the collector. An output DC blocking capacitor and an output matching network are provided between the above third harmonic parallel resonance network and the output end of the power amplifier circuit.
Further, in the above-mentioned circuit structure for improving the linearity and power-added efficiency of the power amplifier, the power amplifier circuit is a Cascode (emitter-based) including an emitter input transistor and a base output transistor. )structure. Of course, in other types of power amplifier circuits, the above-mentioned second harmonic series resonance network and third harmonic parallel resonance network can also be connected between the collector of the output transistor and the output port, thereby improving the linearity and performance of the power amplifier. power-added efficiency purposes. Further, in the above-mentioned circuit structure for improving the linearity and power-added efficiency of the power amplifier, a second harmonic parallel resonance network is connected between the base of the output transistor of the Cascode structure and the ground, that is, the second harmonic The input terminal of the parallel resonant network is connected to the base of the output transistor, and the output terminal is connected to ground. It increases the gain of the fundamental frequency signal and suppresses the second harmonic signal. Further, in the above-mentioned circuit structure for improving the linearity and power-added efficiency of the power amplifier, the second harmonic parallel resonance network includes a second capacitor connected in parallel between the base of the output transistor and the ground and a fundamental frequency series resonance. network. Further, in the above-mentioned circuit structure for improving the linearity and power-added efficiency of the power amplifier, the fundamental frequency series resonance network includes a first inductor and a third capacitor connected in series. The advantages of the present invention are: 1. The second harmonic series resonance network and the third harmonic parallel resonance network in the Cascode structure power amplifier output transistor collector are connected in sequence, which can be used to improve the linearity and power-added efficiency of other types of power amplifiers. . 2. The Cascode circuit of the present invention connects the second harmonic parallel resonance network to the base of the output transistor, thereby improving the gain of the Cascode circuit to the fundamental frequency signal and suppressing the gain of the Cascode circuit to the second harmonic signal. 3. The second harmonic parallel resonance network connected to the base of the output transistor of the Cascode circuit of the present invention can be used to suppress the Hth harmonic signal.
Brief Description of the Drawings
The present invention will be further described below in conjunction with the accompanying drawings and embodiments. Figure 1 is a schematic diagram of the circuit structure of a specific embodiment of the present invention; Figure 2 is a specific embodiment of the present invention. Schematic diagram of the operation of the second harmonic parallel resonance network; Figure 3 is a schematic diagram of the network structure connected to the collector of the output transistor in a specific embodiment of the present invention; Figure 4 is a schematic diagram of the output voltage of the collector of the output transistor superimposed with the third harmonic in a specific embodiment of the present invention. Waveform schematic diagram; Figure 5 is a schematic diagram comparing the collector current waveforms before and after the third harmonic is superimposed on the collector output of the output transistor according to a specific embodiment of the present invention. Among them, C1 is the first capacitor; C2 is the second capacitor; C3 is the third capacitor; C4 is the fourth capacitor; C5 is the fifth capacitor; C6 is the DC blocking capacitor; Ll is the first inductor; L2 is the second inductor; L3 is the third inductor; Ql input transistor; Q2 output transistor; Rl resistor.
Specific embodiments are shown in Figures 1 and 2. This embodiment is a Cascode power amplifier circuit. The Cascode power amplifier includes an input transistor Q1 and an output transistor Q2. The input transistor The base of Ql is connected to the input port of the power amplifier, and a first capacitor Cl is also connected between the input port and the base of the input transistor. The emitter of the input transistor Ql is grounded, and the collector is connected in series with the emitter of the output transistor Q2. The base of the output transistor Q2 is connected to the input end of the second harmonic parallel resonant network, and the output end of the second harmonic parallel resonant network is grounded; the collector of the output transistor Q2 passes through the second and third harmonics in sequence. The resonant network and the output matching network are connected to the output port of the power amplifier. The second harmonic parallel resonance network includes a second capacitor C2 connected in parallel between the base of the output transistor Q2 and ground and a fundamental frequency series resonance network; the network resonates in parallel at the second resonance frequency point. The fundamental frequency series resonance network includes a first inductor L1 and a third capacitor C3 connected in series, and the network resonates in series at the fundamental frequency resonance frequency point.
As shown in Figures 1 and 3, the second and third harmonic resonance networks include a second harmonic series resonance network and a third harmonic parallel resonance network whose input terminals are respectively connected to the collector of the output transistor Q2, so The output end of the second harmonic series resonance network is connected to the ground, and the output end of the third harmonic parallel resonance network is connected to the output matching network and DC blocking capacitor C6 and then connected to the output port of the power amplifier. The second harmonic series resonance network includes a fourth capacitor C4 and a second inductor L2 connected in series between the collector of the output transistor Q2 and ground, and the network resonates in series at the second resonance frequency point. The third harmonic parallel resonance network includes a fifth capacitor C5 and a third inductor L3 connected in parallel between the collector of the output transistor Q2 and the output matching network of the power amplifier. The network resonates in parallel at the third resonance frequency point. The high-frequency small-signal equivalent model of output transistor Q2 is shown in Figure 2. It can be seen from this figure that the output current of the transistor collector is determined by the voltage Ube divided by the transconductance, Rbb, and when 8_ remains unchanged, the size of Ube determines the size of the current generated by the voltage-controlled current source. It can be seen from Figure 2 that IV gt; Rbb, the equivalent impedance of the series and the second harmonic parallel resonant network divides the AC signal amplified by the input transistor Ql, and the voltage divided by Rbe and Rbb is Ube0 For the fundamental frequency signal, the fundamental frequency series resonance network in the second harmonic parallel resonance network resonates, and its impedance is the minimum value R1. At this time, the second harmonic parallel resonance network is equivalent to the parallel connection of Rl and the second capacitor C2. Since Rl is much smaller than the reactance of the second capacitor C2, the impedance of the network is mainly determined by Rl. Since the equivalent impedance of the second harmonic parallel resonant network becomes smaller and Ube is improved, the fundamental current output by the collector of the fundamental transistor Q2 increases, which increases the gain of the fundamental signal. For the second harmonic signal, the second harmonic parallel resonance network resonates in parallel, and the equivalent impedance of the network is the maximum value. At this time, Ute decreases. Therefore, the second harmonic current output from the collector of the output transistor Q2 is reduced, and the second harmonic signal is suppressed. As shown in Figure 3, in this embodiment, the AC signal amplified by the output transistor Q2 is output from the collector of the output transistor Q2. It is filtered by the second harmonic series resonance network and then reaches the output matching network through the third harmonic parallel resonance network. . The second harmonic series resonance network short-circuits the second harmonic signal to the ground, effectively suppressing the second harmonic, so that the amplitude of the second harmonic component in the collector voltage of the output transistor Q2 is very small and can be approximately ignored, improving improves the linearity of the power amplifier. In addition, while ensuring that the fundamental frequency series resonance network resonates at the fundamental wave signal, adjusting the values ??of the first inductor Li, the second capacitor C2 and the third capacitor C3 can make the second harmonic parallel resonance network resonate at the required level. Hth harmonic frequency, thereby suppressing the gain of the Hth harmonic signal. The formula that the network that suppresses the H-th harmonic signal must satisfy is: In this formula, Fo is the fundamental frequency and Fn is the H-th harmonic frequency. The third harmonic parallel resonant network is equivalent to an open circuit for the third harmonic, reflecting the third harmonic signal back to the collector. As shown in Figure 4, adjusting the third inductor L3 and the fifth capacitor C5 in the third harmonic parallel resonance network can make the third harmonic component and the fundamental wave component superimpose in phase at the collector, so that the output voltage waveform at the collector of the output transistor Q2 changes into a shape similar to a square wave. As shown in Figure 5, the superimposed third harmonic causes the transistor that has entered the saturation region to work again in the amplification region, increasing the amplitude of the collector current that was originally depressed due to saturation of the transistor, thereby increasing the output power and power of the power amplifier. Additional efficiency. In addition, the third harmonic parallel resonance network suppresses the output of the third harmonic signal and improves the linearity of the power amplifier. To sum up, the fundamental frequency series resonance network in the second harmonic parallel resonance network improves the gain of the power amplifier to the fundamental frequency signal. The second harmonic parallel network and the second harmonic series network effectively suppress the amplification and output of the second harmonic signal and improve the linearity of the Cascode power amplifier.
After the third harmonic signal is reflected by the third harmonic parallel resonant network, the collector of the base transistor of the Cascode amplifier is superimposed in phase with the fundamental signal, causing the collector voltage waveform to change into a shape similar to a square wave. Due to the change in the collector voltage waveform, the amplitude of the collector current is increased, thereby improving the output power and power-added efficiency of the power amplifier. In addition, the third harmonic parallel resonance network suppresses the transmission of the third harmonic signal to the load, improving the linearity of the power amplifier. The present invention controls harmonic signals by utilizing a series-parallel network of capacitors and inductors, which not only improves the output power and power-added efficiency of the power amplifier, but also significantly improves the power amplifier's static power consumption without increasing the static power consumption of the power amplifier. linearity.
Claims
A circuit structure for improving the linearity and power-added efficiency of a power amplifier. The power amplifier is provided with an output transistor (Q2), characterized in that the output transistor The second harmonic series resonance network that suppresses the output of the second harmonic signal is connected between the collector of (Q2) and the ground, and the third harmonic is connected between the collector of the output transistor (Q2) and the output matching network. The signal is reflected back to the collector's third harmonic parallel resonant network.
2. The circuit structure for improving the linearity and power-added efficiency of the power amplifier according to claim 1, characterized in that the second harmonic series resonance network includes the output transistor (Q2) The fourth capacitor (C4) and the second inductor (L2) connected in series between the collector and the ground resonate to the second harmonic.
3. The circuit structure for improving linearity and power-added efficiency of a power amplifier according to claim 1 or 2, characterized in that the third harmonic parallel resonance network is connected from the output transistor (Q2) The fifth capacitor (C5) and the third inductor (L3) connected in parallel between the collector and the output matching network of the power amplifier resonate to the third harmonic.
4. The circuit structure for improving the linearity and power-added efficiency of a power amplifier according to claim 3, characterized in that the power amplifier circuit is composed of an input transistor (Ql) and a The basic output transistor (Q2) is a Cascode structure formed by stacking in series.
5. The circuit structure for improving the linearity and power-added efficiency of the power amplifier according to claim 4, characterized in that the base connection of the output transistor (Q2) of the Cascode structure has the ability to improve the fundamental frequency. Second harmonic parallel resonance network that increases signal gain and suppresses second harmonic signal output.
6. The circuit structure for improving the linearity and power-added efficiency of the power amplifier according to claim 5, characterized in that the second harmonic parallel resonance network includes a base from the output transistor (Q2) The second capacitor (C2) connected in parallel from pole to ground and the fundamental frequency series resonance network resonate to the second harmonic.
7. The circuit structure for improving linearity and power-added efficiency of a power amplifier according to claim 6, characterized in that the fundamental frequency series resonance network includes a circuit from the output transistor (Q2) to ground The third capacitor (C3) and the first inductor (Li) are connected in series.