1. 1 current and electrostatic discharge
1. 1. 1 current and static electricity
1. 1.2 electrostatic discharge
1. 1.3 Major ESD patents, inventions and innovations
1. 1.4 ESD failure mechanism
1.2 Basic concepts of ESD design
ESD design concept
1.2.2 Response of equipment to external events
1.2.3 optional circuit loop
1.2.4 switch
1.2.5 current path decoupling
1.2.6 Decoupling of feedback loop
1.2.7 Power rail decoupling
1.2.8 local and global distribution
1.2.9 Use of parasitic elements
1.2. 10 buffer
1.2. 1 1 ballast
1.2. 12 Unused part of semiconductor device, circuit or chip function.
1.2. 13 impedance matching between floating and non-floating networks
1.2. 14 Unconnected structure
1.2. 15 Use of Virtual Structure and Virtual Circuit
1.2. 16 Non-shrinking source event
1.2. 17 area effectiveness
1.3 time constant
1.3. 1 electrostatic and magnetostatic time constants
1.3.2 thermal time constant
1.3.3 thermophysical time constant
1.3.4 semiconductor device time constant
1.3.5 Circuit time constant
1.3.6 Chip-level time constant
1.3.7 ESD time constant
1.4 Capacitance, resistance, inductance and ESD
1.4. 1 capacitor
1.4.2 resistor
1.4.3 inductance
1.5 ESD and rule of thumb
1.6 lumped distribution analysis and ESD
1.6. 1 current and voltage distribution
1.6.2 centralized system and distributed system
1.6.3 distributed system: ladder network analysis
1.6.4 resistance-inductance-capacitance (RLC) distributed system
1.6.5 RC distributed system
1.6.6 resistance-conductance (RG) distributed system
1.7 ESD measurement and quality factor
1.7. 1 chip-level ESD measurement
1.7.2 circuit-level ESD measurement
1.7.3 ESD device measurement
1.7.4 commercial measurement of ESD quality and reliability
Twelve-step formation method of 1.8 ESD scheme
1.9 Summary of this chapter
utilize
refer to
Chapter 2 Design Synthesis
2. 1 Structure and synthesis of ESD protection for semiconductor chips
2.2 Electrical connection and spatial connection
2.2. 1 electrical connection
Thermal connection
2.2.3 Spatial connection
2.3 ESD protection, latch-up effect and noise
2.3. 1 noise
cmos latch up
2.4 interface circuits and ESD components
2.5 ESD power clamp network
2.6 ESD rail-to-rail devices
2.6. 1 ESD rail-to-rail network layout
2.6.2 peripheral devices and array I/O.
2.7 protection ring
2.8 Pads, Floating Pads and Connectionless Pads
2.9 Structure under Connection Pad
2. 10 Summary of this chapter
utilize
refer to
Chapter 3 ESD design: MOSFET circuit design
3. 1 Basic ESD design concept
3. 1. 1 channel length and line width control
3. 1.2 ACLV control
3. Esd design example of1.3 MOSFET
3.2 ESD MOSFET design: channel width
3.3 ESD MOSFET design: contact hole
3.3. 1 distance from gate to contact hole
Contact hole spacing
Terminal contact
3.3.4 Contact hole of single finger edge
3.4 ESD MOSFET design: metal distribution
3.4. 1 MOSFET Metal Wire Design and Current Distribution
3.4.2 MOSFET ladder network model
3.4.3 MOSFET connection: non-parallel current distribution
3.4.4 MOSFET connection: parallel current distribution
3.5 ESD MOSFET design: silicide mask plate
Silicide mask design
3.5.2 Design of silicide mask across source and drain
3.5.3 Design of silicide mask covering gate
Silicide and segmentation
3.6 ESD MOSFET design: series * * * source * * gate structure.
3.6. 1 series MOSFET with * * * source * * gate structure
3.6.2 Complete * * * source * * gate MOSFET
3.7 ESD MOSFET design: interdigital design of coupling and ballast technology.
3.7. 1 MOSFET, whose gate is grounded through ballast resistor.
3.7.2 MOSFET with ballast resistance between gate and soft substrate ground.
3.7.3 MOSFET structure with source-gate coupled domino ballast resistor
3.7.4 interdigital structure of bootstrap ballast resistor of MOSFET source start gate
3.7.5 MOSFET source start-up gate bootstrap interdigital MOSFET with diode resistance ballast.
3.8 ESD MOSFET design: design parameters of closed drain
3.9 ESD MOSFET interconnection ballast design
3. 10 MOSFET design: source and drain division
3. 1 1 Summary of this chapter
utilize
refer to
Chapter 4 ESD design: diode design
4. 1 ESD diode design: the basis of ESD
4. Basic concepts of1.1ESD design
4. 1.2 ESD diode design: working principle of ESD diode
4.2 ESD diode design: anode
P+0 width effect of anode diffusion
P+ anode contact
4.2.3 Edge design of P+anode metal silicide region
4.2.4 Isolation distance between P+anode and n+ cathode
4.2.5 Edge effect of P+anode
4.2.6 Design of Circular and Octagonal ESD Diodes
4.3 ESD diode design: interconnection line
4.3. 1 Parallel Wiring Design
4.3.2 Anti-parallel wiring design
4.3.3 Quantization of Tapered Parallel and Anti-parallel Wiring
4.3.4 Continuous Tapered Anti-parallel and Parallel Wiring
4.3.5 Design of Vertical (Side) Wiring with Central Feed
4.3.6 Uniform vertical (lateral) design of metal width
4.3.7 T-shaped extension vertical (side) wiring
4.3.8 Metal Design under the Pad
4.4 ESD diode design: diode design defined by polysilicon.
4.5 ESD diode structure design: N-well diode design
4.5. 1 n well diode connection design
4.5.2 n-well contact density
4.5.3 n-well ESD design, protection ring and adjacent structure
4.6 ESD diode design: n+/p substrate diode design.
4.7 ESD diode design: diode string
4.7. 1 ESD design: diode string current-voltage relationship
4.7.2 Diode string elements in multi-input/output environment
Pad integration
4.7.4 ESD design: diode string design-Darlington amplifier.
4.7.5 ESD design: diode string design-area ratio
4.8 ESD diode design: triple-well diode
4.9 ESD design: BICMOS ESD design
4.9. 1 p+/n well diode ESD structure with high resistance injection collector.
4.9.2 p+/n well diode defined by STI with deep trench (DT) isolation structure.
4.9.3 p+/n well diode defined by STI with trench (TI) isolation structure.
4. 10 Overview of this chapter
utilize
refer to
Chapter 5 ESD design of silicon on insulator
5. Basic concept of1SOI ESD
5.2 SOI ESD design: MOSFET (T-shaped layout with body contact)
5.3 SOI ESD design: SOI lateral diode structure
5.3. 1 SOI lateral diode design
5.3.2 Perimeter design of SOI lateral diode
5.3.3 Channel length design of SOI lateral diode
5.3.4 SOI lateral diode p+/n-/n+ diode structure
5.3.5 SOI lateral diode p+/p-/n+ diode structure
5.3.6 SOI lateral diode p+/p-/n-/n+ diode structure
5.3.7 Gate-free SOI lateral p+/p-/n-/n+ diode structure
5.3.8 SOI lateral diode structure and SOI MOSFET halo
5.4 SOI ESD design: Buried resistance (BR) element
5.5 SOI ESD design: SOI dynamic threshold voltage MOSFET(DTMOS)
5.6 SOI ESD Design: Double Gate (DG)MOSFET
5.7 SOI ESD design: FINFET (non-planar double gate) structure.
5.8 SOI ESD design: substrate structure
5.9 SOI ESD design: SOI-to-body contact structure
5. 10 Summary of this chapter
utilize
refer to
Chapter 6 Off-Chip Drive (OCD) and ESD
6. 1 Off-Chip Drive (OCD)
6. 1. 1 OCD I/O standard and ESD
6. 1.2 OCD: ESD design basis
6. 1.3 OCD: CMOS asymmetric pull-up/pull-down.
6. 1.4 OCD: CMOS symmetric pull-up/pull-down.
6. 1.5 OCD: transmit and receive circuit logic (GTL)
6. 1.6 OCD: high-speed transceiver logic (HSTL)
6. 1.7 OCD: Stub Series Termination Logic (SSTL)
6.2 Off-chip drive: mixed voltage interface
6.3 Off-chip Driving Self-bias Well OCD Network
6.3. 1 OCD: self-biased trap OCD network
6.3.2 ESD protection network of self-biased well OCD network
6.4 Off-chip driver: pipeline OCD network.
6.4. 1 OCD: programmable impedance (pimp) OCD network.
6.4.2 ESD input protection network for pimping obsessive-compulsive disorder
6.5 Off-chip driver: general OCD
6.6 off-chip driver: OCD design of gate array
6.6. Design and implementation of1gate array OCD ESD
6.6.2 OCD Design of Gate Array: Using Unused Components
6.6.3 OCD design of gate array: impedance matching of unused components
6.6.4 OCD ESD design: refers to the power rail on MOSFET.
6.7 Off-chip drive: grid modulation network
6.7. 1 OCD gate modulation MOSFET ESD network
6.7.2 OCD simplifies the power grid modulation network
6.8 off-chip drive ESD design: synthesis of coupling and ballast technology
6.8. 1 MOSFET, bootstrap resistor ballast with diode source starting gate refers to MOSFET.
6.8.2 MOSFET source start-up gate bootstrap resistance ballast refers to MOSFET.
6.8.3 Gate-coupled domino effect resistance ballast MOSFET
6.9 Design of off-chip drive ESD: substrate modulation resistor ballast MOSFET.
6. 10 Summary of this chapter
utilize
refer to
Chapter 7 Receiving Circuit and ESD
7. 1 receiving circuit and ESD
7. 1. 1 receiving circuit and its delay
7. 1.2 receiver circuit performance and ESD load effect
7.2 Receiving Circuit and ESD
7.2. 1 Receiving Circuit and HBM
7.2.2 Receiving Circuit and CDM
7.3 Receiving Circuit and Its Development
7.3. 1 Receiving circuit with half-pass transmission gate
7.3.2 Receiving Circuit with All-pass Transmission Gate
7.3.3 Receiving Circuit, Semi-pass Transmission Gate and Holding Network
7.3.4 Receiving circuit, half-pass transmission gate and improved keeper network
7.4 receiving circuit of pseudo-zero VT half-pass transmission gate
7.5 Zero Transmission Gate Receiving Circuit
7.6 Discharge Transistor Receiving Circuit
7.7 Receiving Circuit with Test Function
7.8 Receiving Circuit of Schmidt Trigger Feedback Network
7.9 Bipolar Transistor Receiving Circuit
7.9. 1 bipolar single-ended receiving circuit
7.9.2 Bipolar differential receiving circuit
7. 10 Summary of this chapter
utilize
refer to
Chapter 8 SOI ESD Circuit and Design Integration
8. 1 SOI ESD design integration
8. Advantages of1.1SOI ESD design over bulk CMOS ESD design.
8. Shortcomings of1.2 SOI in ESD design layout compared with bulk CMOS.
8. 1.3 SOI design layout: T-shaped layout style
8. 1.4 SOI design layout: mixed voltage interface (MVI)T layout style.
8.2 SOI ESD design: diode design
8.3 SOI ESD diode design: mixed voltage interface (MVI) environment
8.4 SOI ESD network in SOI CPU with aluminum interconnection
8.5 SOI ESD design of copper (Cu) interconnection
8.6 SOI ESD design in gate circuit
8.7 SOI and dynamic threshold ESD network
8.8 SOI technology and various ESD problems
8.9 Overview of this chapter
utilize
refer to
Chapter 9 ESD power clamp
9. 1 ESD power supply clamp design standard
9.2 ESD power clamp: based on diode
9.2. 1 ESD power clamp: series diode as the core clamp.
9.2.2 ESD power clamp: series diode as the core clamp-metal cladding design concept
9.2.3 ESD power supply clamping: series diode as the core clamping-boosting design concept.
9.2.4 ESD power clamp: series diode string as the core clamp-cantilever design concept.
9.2.5 ESD power clamp: Three-well series diode is used as the core clamp.
9.2.6 ESD power supply clamp: SOI series diode ESD power supply clamp.
9.3 ESD power clamp: based on MOSFET
9.3. 1 CMOS RC triggers MOSFET ESD power clamp.
9.3.2 Mixed voltage interface RC triggers ESD power supply clamping.
9.3.3 Voltage Triggered MOSFET ESD Power Clamping
9.3.4 Improved RC Triggered MOSFET ESD Power Clamping
9.3.5 MOSFET Power Clamping Layout Triggered by RC Network
9.4 ESD power clamp: based on bipolar transistor
9.4. 1 bipolar ESD power clamp: voltage triggered ESD power clamp.
9.4.2 Bipolar ESD power clamp: triggered by Zener breakdown voltage.
9.4.3 Bipolar ESD power supply clamp: BVCEO voltage triggers ESD power supply clamp.
9.4.4 Bipolar ESD power clamp: forward bias voltage of mixed voltage interface and BVCEO breakdown integration.
Bipolar ESD power clamp
9.4.5 Bipolar ESD power supply clamp: triggered by ultra-low voltage forward bias voltage.
9.4.6 Bipolar ESD power supply clamp: capacitor trigger
9.5 ESD power clamp: silicon controlled rectifier based on rectifier.
9.6 Overview of this chapter
utilize
refer to