On August 6th, an invention patent named chip packaging structure, electronic equipment, chip packaging method and packaging equipment applied by Huawei was made public.
application publication number: CN113228268A
application number: CN21881493.2
classification number: H1L23/ 538
Classification: Basic Electrical Components
Publication (Announcement)No.: CN113228268A
Publication (Announcement) Date: 221-8-6
Invention Name: Chip Packaging Structure, Electronic Equipment, Chip Packaging Method and Packaging Equipment
Inventor: Guo Mao; Li Wei; Zhang Xiaodong
Applicant: Huawei Technologies Co., Ltd.
Application date: 218-12-29
Application date: 221-8-6
A means trial stage, and it has not been authorized.
In combination with their recent introduction of chip engineers, it is speculated that Chrysanthemum Factory should make efforts to manufacture chips. It is not clear whether it includes the manufacturing process or whether the manufacturing relies on SMIC.
Abstract:
The application provides a chip packaging structure, electronic equipment, a chip packaging method and packaging equipment, including a chip and a substrate, wherein the first surface of the chip is provided with a first electrical connector, the first surface of the substrate is provided with a first passivation layer, the first passivation layer is provided with a groove, and a second electrical connector is electroplated inside the groove. The first electrical connector of the chip and the second electrical connector arranged inside the first passivation layer are directly electrically connected, and the thickness of the first passivation layer is relatively thin, so that the communication path between the chip and the substrate is effectively reduced, the electrical conductivity between the chip and the PCB board is improved, and the cost of the chip packaging structure is effectively reduced.
China is also an important base for chip packaging and testing. There are four leading chip packaging and testing enterprises, namely Changdian Technology, Tongfu Microelectronics, Tianshui Huatian Technology and Jingfang Technology. Chip manufacturing is divided into three links, namely, upstream design link, midstream manufacturing link and downstream sealing and testing link. Compared with design and manufacturing, the technical difficulty of sealing and testing is relatively low.
Because the chip packaging and testing technology is relatively difficult, economies of scale will become possible. Therefore, all the major packaging and testing enterprises in the world are basically located in the densely populated Asia-Pacific region. And driven by the cost and supporting facilities, almost all the packaging and testing enterprises in the world began to set up factories in China, which led to the increase of the packaging and testing output value of mainland chips at an average annual compound growth rate of 2%, and the industrial transfer trend was basically determined.
attach the integrated circuit industry chain.
Come on, my country. Get rid of the chip manufacturing bottleneck problem as soon as possible.