The patent abstract shows that the application relates to the field of electronic technology and is used to solve the problem of how to reliably bond multiple sub-chip stacked units to the same main chip stacked unit.
The patent document shows that the chip stacked package structure includes:
The main chip stacking unit has a plurality of main pins which are insulated and arranged on the first surface at intervals.
A first bonding layer disposed on the first surface; The first bonding layer comprises a plurality of insulating bonding parts arranged at intervals;
Each of a plurality of combining parts comprises at least one combining part, and any two combining parts are arranged in an insulating manner, and the cross-sectional areas of any two combining parts are the same; A plurality of bonding elements are respectively bonded with a plurality of main pins;
A plurality of sub-chip stacking units arranged on the surface of the first bonding layer on the side away from the main chip stacking unit;
The sub-chip stacking unit is provided with a plurality of insulating micro bumps arranged at intervals; Each of a plurality of microprojections is bonded to one of a plurality of bonding members.