VERSION 5.5； Version description
namecasesitiveon; LEF format is case-sensitive.
BUSBITCHARS "< >" ; Set the definition bus identifier, and the port name is x <; 1> ,X< 2> ,...X< n> Will be regarded as bus
units
database micros1; Setting defines that 1 micron is divided into 1 units, which is the value of unit length.
END UNITS
LAYER metal1? Set the defined layer as metal 1 layer, and the following is the specific details of the defined metal 1 layer.
TYPE ROUTING; ? Define metal1 for routing
WIDTH .1; Define metal layer 1 as wiring metal, and the default line width is .1 um
SPACING .3; ? Define the trace spacing of metal layer 1 as .3um
PITCH 1.2; Define the distance from the metal layer 1 to the through hole as 1.2
DIRECTION HORIZONTAL; The wiring direction of metal layer 1 is horizontal.
CAPACITANCE CPERSQDIST .14； This setting defines the capacitance of each block (1x1um).
RESISTANCE RPERSQ .4； Set the square resistance of each metal.
END metal1
LAYER via
TYPE CUT; Define via as the CUT type under layout and wiring, that is, through holes of Metal1 and Metal2
END via
LAYER metal2. This setting defines metal 2, which is similar to the setting of metal 1 above.
TYPE ROUTING ;
WIDTH .3 ;
SPACING .3 ;
PITCH 1.2 ;
DIRECTION VERTICAL ; This setting is different from metal layer 1, and the wiring direction is vertical.
CAPACITANCE CPERSQDIST .12 ;
RESISTANCE RPERSQ .2 ;
endmetal2
viam1 _ poly1defaule this setting defines how to generate a via, where a via between metal and poly1 is generated by default. The through hole generated here is generated when the upper and lower floors are both default width. When the upper and lower floors are not the default width, there are other rules to define.
LAYER poly1;
RECT -.3 -.3 .3 .3 ; Sets the shape that defines Poly1.
LAYER cont;
RECT -.15 -.15 .15 .15; Sets the shape that defines the cont (contact hole).
LAYER metal1;
RECT? -.3 -.3 -.3 .3; Setting defines the shape of metal1
endm1 _ poly1
viam2 _ m1default This setting defines the through hole between metal1 and metal2 by default. Similar to the above through hole arrangement.
LAYER metal1 ;
RECT -.3 -.3 .3 .3 ;
LAYER via ;
RECT -.15 -.15 .15 .15 ;
LAYER metal2 ;
RECT -.3 -.3 .3 .3 ;
END M2_M1
VIA M3_M2 DEFAULT this setting defines the through hole between metal2 and metal3.
LAYER metal2 ;
RECT -.3 -.3 .3 .3 ;
LAYER via2 ;
RECT -.15 -.15 .15 .15 ;
LAYER metal3 ;
RECT -.3 -.3 .3 .3 ;
endm3 _ m2
via rule viagen 21 generate is different from the previous through hole setting, which defines the rules for generating through holes under non-default conditions.
LAYER metal1 ;
DIRECTION HORIZONTAL ;
OVERHANG .3 ;
metaloverhang . ;
LAYER metal2 ;
DIRECTION VERTICAL ;
OVERHANG .3 ;
metaloverhang . ;
LAYER via ;
RECT -.15 -.15 .15 .15 ;
SPACING .6 BY .6 ;
END VIAGEN21
SITE standard this setting defines various sites, and the site of the standard unit is defined here.
SYMMETRY y ;
CLASS core ;
SIZE 1.2 BY 1.8 ;
END standard
SITE IO this setting defines the site of the IO unit.
SYMMETRY y ;
CLASS pad ;
SIZE 21.5 BY 7.8 ;
END IO
SITE corner this setting defines the site of the pad at the four corners of the chip.
CLASS pad ;
SIZE 7.8 BY 7.8 ;
SYMMETRY y r9 ;
END corner
SITE SBlockSite this setting defines the site of a hard-core unit block, which is used for blocks, such as ram/rom and hardip.
CLASS core ;
SIZE 1. BY 1. ;
END SBlockSite
the LEF above defines various layout and routing rules, and the tools make layout and routing according to these rules. The above LEF means that LEF data with similar process file properties is used by layout and routing tools.
the geometric information of various cell is defined below, which is provided for the layout and routing tools.
MACRO AOI21_B this setting defines the LEF information of unit AOI21_B.
ORIGIN . . ; This setting defines the origin coordinates.
SIZE 6. BY 1.8 ; This setting defines the cell size in um
SYMMETRY x y; The setting definition tool can rotate the unit in the X-Y direction.
SITE standard ; This setting defines standard SITE, which indicates that the unit type is standard unit, and other types include IO, so the site is IO.
CLASS CORE ; This setting defines that the unit is used in the chip kernel instead of being placed in the IO location.
PIN vdd! This setting defines the name of the power supply pin vdd! .
USE POWER ; This setting defines vdd! It's for power.
DIRECTION INPUT ; This setting defines vdd! It's the input PIN.
SHAPE FEEDTHRU ;
PORT
LAYER metal1 ; This setting defines the vdd of the cell! The shape of. .
RECT . 9.15 6. 1.65 ; This setting defines vdd! Rectangular shape parameters of metal 1 layer RECT based on.
END
END vdd!
PIN gnd! This setting defines the ground wire name pin gnd! .
USE GROUND ; This setting defines gnd! Used for the ground.
DIRECTION INPUT ; This setting defines gnd! It's the input PIN.
SHAPE ABUTMENT ;
PORT
LAYER metal1 ;
RECT . .15 6. 1.65 ; This setting defines gnd! Rectangular shape parameters of metal 1 layer RECT based on.
END
END gnd!
PIN Y this setting defines PIN foot Y ..
DIRECTION OUTPUT ; This setting defines y as the output.
PORT
LAYER metal1 ;
RECT 4.12 2.32 4.28 2.48 ; This setting defines the shape of y in the metal 1 layer.
RECT 5.32 8.32 5.48 8.48 ;
RECT 5.32 7.12 5.48 7.28 ;
RECT 5.29 5.89 5.51 6.11 ;
RECT 5.29 4.69 5.51 4.91 ;
RECT 5.29 3.49 5.51 3.71 ;
LAYER cont ;
RECT 4.5 3.15 4.35 3.45 ;
RECT 4.5 2.25 4.35 2.55 ;
RECT 5.25 8.1 5.55 8.4 ;
RECT 5.25 7.2 5.55 7.5 ;
END
END Y
OBS This setting defines the parameters of the OBStruct, that is, the area defined below cannot be wired (in this case, metal1).
LAYER metal1 ;
RECT 5.9 1.95 5.85 2.71 ;
RECT 5.9 3.29 5.85 3.91 ;
RECT 5.9 4.49 5.85 5.11 ;
RECT 5.9 5.69 5.85 6.31 ;
RECT 5.9 6.89 5.85 7.51 ;
LAYER via ; This setting defines where the layout tool cannot punch holes.
RECT 5.28 7.8 5.52 7.32 ;
RECT 5.28 8.28 5.52 8.52 ;
RECT 4.8 2.28 4.32 2.52 ;
end
end aoi21 _ b
end library
1, SITE
SITE standard this setting defines the site.
SYMMETRY y ;
CLASS core ;
SIZE 1.2 BY 1.8 ;
END standard
site is the smallest geometric unit in the identification unit of layout and routing tools. There may be several sites in a design. site standard refers to the site of standard unit and site IO refers to the site of IO pad. Generally speaking, the height of the cell is certain, which is equal to the height of the site, and the width of the cell is an integer multiple of the site.
2, Via rule
via rule, when wiring, wires of different layers need to be connected, and different vias need to be generated in different situations. What kind of vias are generated is determined by the via rule in LEF.
3, pitch
pitch is an important concept in LEF, which defines the future wiring spacing and has a great
influence on the wiring effect. Pitch is the distance between metals in the same layer. Layout and wiring is a grid router, and the smallest grid of its wiring is a pitch, as shown in the following figure.
the signal line runs along the grid, and the pitch is greater than or equal to line to via spacing, that is to say, it is guaranteed that one grid point runs the line, and the adjacent grid points are punched, and the spacing between holes and lines does not violate the spacing rules. In multi-layer wiring, it is generally defined that the pitch of each layer is the same or keeps a simple relationship, such as 1:2, so as to ensure good wiring effect. The size of pitch must be carefully considered.
4, abstract
A complete version of a cell contains information of all layers, but in the use of layout and routing tools, it doesn't need so much information. Layout and routing tools only need to know the location of the pin, where it can't be routed, and so on, which can reduce the amount of data and improve the processing speed.
as shown in the figure below is the layout of a cell and the graphic description of its LEF. Layout and routing will be routed with the abstract information of the cell.
From: LEF format-Spring Breeze Ichiro-Blog Garden (cnblogs.com)