Hmm. How interesting
But I will help you.
Source program and analog waveform:
Library? ieee
Use? IEEE . STD _ logic _ 1 164 . all；
Use? IEEE . STD _ logic _ unsigned . all；
Entity? m6？ be
port(clk，rst:in？ std _ logic
Q:? Out? std_logic_vector(2？ Tonto? 0));
End? M6；
Architecture? bhv？ Yes? m6？ be
Type? Country? is(st0，st 1，st2，st3，st4，st5)；
Signal? Stx: country;
begin
Process (clock)
begin
What if? rst=' 1 '？ then what stx & lt= st0q & lt="000";
Elsfer? Clock event? And then what? clk=' 1 '？ then
Case (stx)? be
What time? st0 = & gtq & lt="000"; stx & lt= ST 1；
What time? st 1= >q & lt="00 1"; stx & lt= st2
What time? st2= >q & lt="0 1 1"; stx & lt= st3
What time? st3= >q & lt=" 1 1 1"; stx & lt= st4
What time? st4= >q & lt=" 10 1"; stx & lt= st5
What time? st5= >q & lt=" 100"; stx & lt= st0
What time? Other =>? stx & lt= st0
End? Case;
End? If;
End? Process;
End? bhv