Patent Name: Manufacturing Method of Cmos Input Buffer
Technical field:
The invention relates to a CMOS input buffer circuit, in particular to a CMOS input buffer circuit based on linear compensation technology. The application fields are CMOS analog integrated circuits and mixed-signal integrated circuits that need high linear input buffer.
Background art:
High linearity CMOS input buffer circuit is of great significance for the design of CMOS analog integrated circuits and mixed-signal integrated circuits. As the interface unit between the input signal and the signal processing circuit, the linearity of the input buffer will directly limit the accuracy index of the system level. Traditional input buffer circuits mostly use BJT devices and adopt emitter follower structure. With the development and large-scale application of modern CMOS technology, the traditional BJT structure has been replaced by CMOS input buffer circuit constructed by CMOS device and source follower structure, as shown in Figure 1 ... Although CMOS process has many advantages over bipolar process, compared with BJT device, the input transconductance and output impedance of CMOS device are lower, and the most important thing is more serious parasitism, and the nonlinear changes of device parameters are significant. Therefore, the linearity of CMOS input buffer is lower than that of traditional structure. Some original techniques for improving the linearity of BJT input buffer circuit are not suitable for CMOS process. In order to improve the linearity of CMOS input buffer circuit, the usual solution is to increase the current value of tail current tube to improve the input transconductance, but this not only increases the layout area of the circuit, but also greatly increases the system power consumption. Based on the above, a linearity improvement technology suitable for CMOS input buffer circuit is needed to meet the design needs of CMOS analog integrated circuits and digital-analog mixed integrated circuits.