The duplexer of the base station seems to be an iris-coupled cavity filter, which is coupled with some cavities. The coupling between input and output is T, which is the connecting part on the resonator, not the coupling loop. The frequency is regulated by capacitance. The filter is a band-pass filter for wide signals.
It would be better if you could see the response speed of the filter.
central processor
Network communication is handled by Freescale MPC832 1 PowerQUICC2 CPU, which runs at 200 MHz and has two 256 MB Hynix DDR2 RAM. It uses PMC Quadrphy10Gb controller for two optical input/output.
The decoding and coding of single bit streams of ADC and DAC are handled by three Altera Cyclone III FPGA and customized Huawei SD6 15 1RBI controllers.
Huawei base station uses Texas Instruments TMS320 series DSP processor to process a single bit stream. TMS320C64 10 is a fixed-point DSP that only calculates integers, and TMS320ct164821GHz DSP CPU calculates floating-point numbers.
Signal receiving part
The input signal comes from two out-of-phase lines. First, it is processed by SkyWorks Sky73021-1.1.7-2.2 GHz down-conversion mixer, and the frequency from 2.2 GHz to 550 MHz is obtained.
The local oscillator of the down-conversion mixer is ADF4 1 10B from analog devices.
SIPAT saw filter is used for isolation.
According to different signal sources or types, it is assumed that the analog device AD8376 variable gain amplifier is used before the signal line is divided into 3G ADC line or 4G ADC line.
The analog-to-digital conversion of 3G lines is handled by analog device AD6655- 10, which is a 14-bit 150 MSPS chip specially designed for 3G base stations.
There are some components in the 4G line, such as bidirectional hswa+110 domain RF switch, which is a dual-channel MAX2039E/dowoconversion mixer and an additional recovery period hswa+110 domain RF switch.
All the time sequences are processed by AD95 16-3 of ADI, which is a 14 output clock generator and a built-in 2 GHz local oscillator.
Signal transmission part
The unit data stream of Altera Cyclone III FPGA is processed by TxDAC AD9788 TXDACs from ADI. The rated MSPS of this device is 16-bit 800.
In order to raise the signal frequency to the broadcast carrier frequency, two ADL5375-05 upconversion modulators from analog devices are used. Their frequencies range from 400 MHz to 6 GHz.
Then, the signal is sent through a five-stage ceramic resonator bandpass filter.
The signal phase can be switched from the setting of transistor and EMC technology and HPJ2F hybrid coupler of Florida RF Laboratory.
The preamplifier before the signal is sent to the power amplifier is Freescale MMG3004NT 1 high linear amplifier, which can amplify 17 dB in the range of 400mhz ~ 2.2 GHz.
In order to control the signal strength, the MCL 3 1R5 digital step attenuator is located in front of the output connector. This is a 3 1.5 dB attenuator, which can be controlled in 0.5 dB steps through a 6-bit serial interface.
power amplifier
The power amplifier adopts two stages. The first stage is Infineon PTMA 180402FL40W RF LDMOS. Two 90-degree non-phase signals are fed into the output stage transistor NXP BLF6G20LS-140140 W RF LDMOS through the Xinger II XC 1900A-03S hybrid coupler.
The output is recombined in the Xinger II XC 1900A-03S hybrid coupler, and then enters the duplexer through the circulator.