History of memory development
Before understanding the development of memory, we should first explain a few common terms, which will help us strengthen our understanding of memory.
RAM is the abbreviation of RandomAccessMemory. It is divided into two types: StaticRAM (static random access memory) and DynamicRAM (dynamic random access memory).
SRAM used to be a major type of memory. SRAM was very fast and could save data without refreshing. It stores data in the form of a bistable circuit with a complex structure. It requires more transistors to form registers to save data. Therefore, the silicon wafer area it uses is quite large and the manufacturing cost is quite high. Therefore, SRAM can only be used in On a cache that is much smaller than main memory. After Intel integrated the L2 cache into the CPU (starting with Medocino), SRAM lost its largest source of application demand. Fortunately, in the development trend of mobile phones from analog to digital, SRAM finally found another source of power-saving advantages. An opportunity for demand growth, coupled with demand incentives for network servers, routers, etc., has allowed the SRAM market to barely continue to grow.
DRAM, as the name implies, is dynamic RAM. The structure of DRAM is much simpler than that of SRAM. The basic structure is composed of a MOS tube and a capacitor. It has the advantages of simple structure, high integration, low power consumption, and low production cost, and is suitable for manufacturing large-capacity memories, so most of the memories we use now are composed of DRAM. So the following mainly introduces DRAM memory. Before describing DRAM memory in detail, we must first talk about the concept of synchronization. According to the memory access method, it can be divided into two types: synchronous memory and asynchronous memory. The criterion for differentiation is whether they can be synchronized with the system clock. The memory control circuit (in the motherboard's chipset, usually in the Northbridge chipset) issues a row address select signal (RAS) and a column address select signal (CAS) to specify which memory bank will be accessed. EDO memory before SDRAM used this method. The time taken to read the data is expressed in nanoseconds. When the speed of the system gradually increases, especially when the 66MHz frequency becomes the bus standard, the speed of EDO memory becomes very slow. The CPU always has to wait for data from the memory, which seriously affects the performance and the memory becomes a big bottleneck. Therefore, SDRAM that synchronizes the system clock frequency appears. Classification of DRAM FPDRAM: also called fast page memory, very popular in the 386 era. Because DRAM requires a constant current to retain information, once the power is turned off, the information is lost. Its refresh frequency can reach hundreds of times per second, but because FPDRAM uses the same circuit to access data, there is a certain time interval between DRAM's access times, which results in its access speed not being very fast. In addition, in DRAM, since the storage address space is arranged in pages, when a certain page is accessed, switching to another page will occupy additional clock cycles of the CPU. Most of its interfaces are 72-line SIMM type. EDODRAM: EDORAM - ExtendedDateOutRAM - external extended data mode memory. EDO-RAM is similar to FPDRAM. It cancels the time interval between the two storage cycles of extended data output memory and transmission memory, and sends the data to the CPU at the same time. Access the next page, so the speed is 15~30% faster than ordinary DRAM. The working voltage is generally 5V, and its interface method is mostly a 72-line SIMM type, but there are also 168-line DIMM types. EDODRAM is popular in 486 and early Pentium computers. The current standard is SDRAM (short for synchronous DRAM), which, as the name suggests, is synchronous to the system clock frequency. SDRAM memory access uses burst mode. Its principle is that SDRAM adds synchronization control logic (a state machine) to the existing standard dynamic memory and uses a single system clock to synchronize all address data and control signals. Using SDRAM can not only improve system performance, but also simplify design and provide high-speed data transmission. Functionally, it is similar to conventional DRAM and also requires a clock to refresh. It can be said that SDRAM is an enhanced DRAM with an improved structure.
However, how does SDRAM use its synchronization characteristics to adapt to the needs of high-speed systems? We know that the dynamic memory technology we used originally was based on asynchronous control. When the system uses these asynchronous dynamic memories, it needs to insert some wait states to adapt to the needs of the asynchronous dynamic memories. At this time, the execution time of the instruction is often determined by the speed of the memory rather than the highest rate that the system itself can achieve. For example, when storing continuous data in CACHE, a fast page memory with a speed of 60ns requires a page cycle time of 40ns; when the system speed runs at 100MHz (one clock cycle 10ns), each time a data access is performed, it needs to wait 4 clock cycles! Using SDRAM, due to its synchronization characteristics, this moment can be avoided. Another major feature of the SDRAM structure is that it supports two columns of DRAM addresses to be opened at the same time. Memory access between two open memory banks can be interleaved. General preset or activation columns can be hidden in the memory bank access process, which allows one memory bank to be read or written at the same time. Preset. By proceeding this way, seamless data rates of 100MHz can be achieved throughout the entire device read or write. Because the speed of SDRAM constrains the clock speed of the system, its speed is calculated in MHz or ns. The speed of SDRAM cannot be slower than the system clock speed at least. SDRAM access usually occurs in four consecutive burst cycles. The first burst cycle requires 4 system clock cycles, and the second to fourth burst cycles only require 1 system clock cycle. The numerical representation is as follows: 4-1-1-1. By the way, BEDO (BurstEDO) is burst EDO memory. In fact, its principle and performance are similar to SDRAM, because Intel's chipset supports SDRAM, and INTEL's market leadership has helped SDRAM become the market standard.
Two interface types of DRAMR There are two main interface types of DRAM, namely early SIMM and current standard DIMM. SIMM is the abbreviation of Single-InLineMemoryModule, which is a single-sided contact memory module. This is the memory interface method commonly used in 486 and earlier PCs. In earlier PCs (before 486), 30-pin SIMM interfaces were mostly used, while in Pentium, 72-pin SIMM interfaces were mostly used, or they coexisted with DIMM interface types. DIMM is the abbreviation of DualIn-LineMemoryModule, which is a double-sided contact memory module. That is to say, there are data interface contacts on both sides of the plug-in board of this type of interface memory. This type of interface mode memory is widely used in current computers, usually It is 84 pins, but because it is bilateral, there are 84 × 2 = 168 lines of contact in one terminal, so people often call this kind of memory 168-line memory, and the 72-line SIMM type memory module is directly called 72 lines of memory. DRAM memory is usually 72 lines, EDO-RAM memory has both 72 lines and 168 lines, and SDRAM memory is usually 168 lines. The arrival of new memory standards in the new century has also brought about major changes in computer hardware. Computer manufacturing technology has developed to the point where it is possible to increase the clock frequency of microprocessors (CPUs) to the edge of one gigabit. The corresponding memory must also keep up with the speed of the processor. There are two new standards now, DDRSDRAM memory and Rambus memory. The competition between them will become the core of competition in the PC memory market. DDRSDRAM represents a path of gradual evolution of memory. Rambus represents a major change in computer design. Seen from a further perspective. DDRSDRAM is an open standard. However, Rambus is a patent. The winner between them will have a significant and far-reaching impact on the computer manufacturing industry.
RDRAM has greatly improved its operating frequency, but this structural change involves comprehensive changes including chipsets, DRAM manufacturing, packaging, testing, and even PCB and modules, which can be said to be far-reaching. The hair moves the whole body.
What is the future development of high-speed DRAM structures?
Can Intel's refurbished and re-released 820 chipset really bring RDRAM to the mainstream? PC133SDRAM: PC133SDRAM is basically just an extension of PC100SDRAM. It continues the old specifications in terms of DRAM manufacturing, packaging, modules, and connectors. Their production equipment is the same, so the production cost is almost the same as PC100SDRAM. Strictly speaking, the difference between the two is only that under the same process technology, there is an additional "screening" process to select particles with a speed of up to 133MHz. If used with a chipset that supports 133MHz FSB and increases the CPU's front-side bus frequency (FrontSideBus) to 133MHz, the DRAM bandwidth can be increased to more than 1GB/sec, thereby improving overall system performance. DDR-SDRAM: DDR SDRAM (Double Data Rate DRAM) or SDRAM II. Because DDR can transmit data on both the rising and falling edges of the clock, the actual bandwidth is doubled, greatly improving its performance/cost ratio. In terms of actual function comparison, the second-generation PC266DDRSRAM (133MHz clock × 2 times data transmission = 266MHz bandwidth) derived from PC133 not only shows that its performance is 24.4% higher than Rambus in the latest InQuest test report, but also in Micron In the test, its performance was also better than other high-bandwidth solutions, fully demonstrating that DDR is capable of competing with Rambus in terms of performance. DirectRambus-DRAM: The big difference between RambusDRAM design and previous DRAM is that its microcontroller is different from general memory controllers, so the chipset must be redesigned to meet the requirements. In addition, the data channel interface is also different from general memory. Rambus transmits data with two data channels (channels) of 8 bits each (9 bits including ECC). Although it is narrower than the 64 bits of SDRAM, its clock frequency can be as high as 400MHz, and it can transmit data on both the rising and falling edges of the clock. data, thus achieving a peak bandwidth of 1.6GB/sec.
Comprehensive comparison of various DRAM specifications Data bandwidth: From the perspective of data bandwidth, the peak data transfer rate of traditional PC100 can reach 800MB/sec when the clock frequency is 100MHz. If DRAM is manufactured with advanced 0.25 micron threads, most PC133 particles with a clock frequency of 133MHz can be "selected", which can increase the peak data transfer rate to 1.06GB/sec again. As long as the CPU and chipset can cooperate, the overall performance can be improved. System performance. In addition, as far as DDR is concerned, since it can transmit data on both the rising and falling edges of the clock, at the same clock frequency of 133MHz, its peak data transmission will be significantly increased by two times, reaching the level of 2.1GB/sec. Its performance Even higher than the 1.6GB/sec that Rambus can achieve at this stage.
Transmission mode: Traditional SDRAM uses parallel data transmission, while Rambus adopts a more special serial transmission method. Under the serial transmission method, data signals come in and out, which can reduce the data bandwidth to 16 bits and greatly increase the operating clock frequency (400MHz). However, this also creates problems in the data transmission design of the module. limit. In other words, in series connection mode, if one of the modules is damaged or has an open circuit, the entire system will not be able to boot normally. Therefore, for a motherboard using Rambus memory modules, the three sets of memory expansion slots must be completely filled. If the Rambus modules are insufficient, only a relay module (ContinuityRIMM Module; C- RIMM), which is purely used to provide signal serial connection work and allow smooth data transmission. Module and PCB design: Since the operating frequency of Rambus is as high as 400MHz, the circuit design, circuit layout, particle packaging and memory module design are all very different from previous SDRAM.
In terms of module design, the memory module composed of RDRAM is called RIMM (RambusInMemoryModule). The current design can be composed of different numbers of RDRAM particles such as 4, 6, 8, 12 and 16. Although the number of pins It has been increased to 184, but the length of the entire module is equivalent to the original DIMM. In addition, in terms of design, each transmission channel of Rambus can carry a limited number of chip particles (up to 32), which results in a limitation in the capacity of the RDRAM memory module. In other words, if you have already installed a RIMM module containing 16 RDARM chips, if you want to expand the memory, you can only install another module with up to 16 RDARM chips. In addition, since the RDARM will generate high temperatures when operating at high frequencies, the RIMM module must be designed with a heat sink, which also increases the cost of the RIMM module.
Particle packaging: DRAM packaging technology has improved from the earliest DIP and SOJ to TSOP. Judging from the current mainstream SDRAM modules, in addition to the TinyBGA technology pioneered by Shengchuang Technology and the BLP packaging mode pioneered by Qiaofeng Technology, the vast majority still use TSOP packaging technology.
With the successive introduction of DDR and RDRAM, the memory frequency has been raised to a higher level. TSOP packaging technology has gradually become unable to meet the requirements of DRAM design. Judging from the RDRAM promoted by Intel, it adopts a new generation of μBGA packaging form. It is believed that the packaging of other high-speed DRAM such as DDR will adopt the same or different BGA packaging form in the future. Although RDRAM has made breakthrough progress in clock frequency, effectively improving the performance of the entire system, in actual use, its specifications are very different from the current mainstream SDRAM, and it is not only incompatible with existing system chips. This has resulted in a situation where Intel is the sole monopoly. Even in the design of DRAM modules, not only the latest generation BGA packaging method is used, but also the strict standards of 8-layer boards are adopted in the design of circuit boards, not to mention the huge investment in test equipment. This makes most DRAM and module manufacturers dare not follow up rashly.
Besides, since Rambus is a patented standard, manufacturers who want to produce RDRAM must first obtain certification from Rambus and pay high patent fees. Not only does this increase the cost burden on DRAM manufacturers, but they are also worried that they will lose their original specification control capabilities when formulating new generation memory standards in the future.
Since the RIMM module can only have a maximum of 32 particles, the application of Rambus is limited and can only be used on entry-level servers and advanced PCs. Perhaps PC133 cannot compete with Rambus in terms of performance, but once DDR technology is integrated, its data bandwidth can reach 2.1GB/sec, which is not only ahead of the 1.6GB/sec standard that Rambus can achieve, but also due to its open Because the standards and compatibility are much higher than Rambus, it is estimated that it will cause great damage to Rambus. What's more, with the strong support of Taiwan's alliances such as VIA and AMD, it is still unknown whether Intel can continue to dominate the market as before. At least, in terms of low-priced PCs and network PCs, the market for Rambus will be small.
Conclusion: Although Intel has adopted various strategic layouts and countermeasures to restore the momentum of Rambus, after all, products with breakthrough specifications like Rambus have many inherent difficulties. problems to overcome. Perhaps Intel can solve the technical problems by changing the RIMM slot method of the motherboard, or proposing a transitional solution (S-RIMM, RIMMRiser) where SDRAM and RDRAM exist together. But when it comes to controlling the cost of large-scale mass production, Intel cannot do it alone. What's more, computer applications under the network trend will become increasingly low-priced. Whether the market demand is interested in Rambus, then Still to be tested.
On the supply side, judging from NEC’s original VCMSDRAM specification (VirtualChannelMemory) and the fact that DRAM major manufacturers such as Samsung have become more conservative in their support for Rambus, coupled with insufficient investment in related packaging and testing equipment, it is estimated that before the end of the year, Rambus memory modules will still lack price competitiveness with PC133 or even DDR. From a long-term perspective, the Rambus architecture may become mainstream, but it will no longer be the absolute mainstream dominating the market. The SDRAM architecture (PC133, DDR) should have very good performance due to its low cost advantages and wide range of application fields. performance. It is believed that the future DRAM market will be a situation where multiple structures coexist.
The latest news is that Rambus DRAM, which is expected to become the main force of the next generation of memory, has suffered a slight setback due to the delay in the launch of the chipset. Many major semiconductor and computer manufacturers around the world are aiming to standardize DDR SDRAM. The AMII (Advanced Memory International Inc.) camp formed by the same party decided to actively promote the standardization of PC1600 and PC2100 DDR SDRAM specifications that are more than 10 times faster than PC200 and PC266. This move has brought the battle for memory dominance between Rambus DRAM and DDR SDRAM into a new stage. new situation. AMD, the world's second largest microprocessor manufacturer, has decided that its Athlon processor will use PC266 DDRSDRAM and will develop a chipset that supports DDRSDRAM before the middle of this year, which greatly encourages the DDRSDRAM camp. Global memory manufacturers are very likely to shift their future investment focus from Rambus DRAM to DDRSDRAM.
To sum up, the development momentum of DDRSDRAM this year will exceed that of RAMBUS. Moreover, the production cost of DDR SDRAM is only 1.3 times that of SDRAM, which is more advantageous in terms of production cost. In addition to DDR and RAMBUS, there are several other promising memory products in the future. Here are some of them: SLDRAM (SyncLinkDRAM, synchronous link memory): SLDRAM may be the closest competitor to RDRAM in terms of speed. SLDRAM is an enhanced and expanded SDRAM architecture that extends the current 4-bank structure to 16 banks and adds new interfaces and control logic circuits
. SLDRAM uses each pulse edge to transfer data like SDRAM.
VirtualChannelDRAM: VirtualChannel "virtual channel" is a type of register installed between the memory unit and the memory control part on the main control chip, which is equivalent to a cache. After using VC technology, when external read and write operations are performed on the memory, the read and write operations on each unit in the memory chip will no longer be directly performed, but will be handled by VC instead. The caching effect of the VC itself cannot be underestimated. When the memory chip capacity is 64Mbit, which is the most common at present, the bandwidth between the VC and the memory unit has reached 1024bit. Even without considering the speed improvement brought by front/background parallel processing, the basic structure of "first moving data from the memory unit to the high-speed VC and then reading and writing externally" is itself very suitable for improving memory performance. Overall speed. Each memory chip can be equipped with multiple VCs, and the total number of VCs in the 64Mbit product is 16. Not only can each VC correspond to a different memory master device (MemoryMaster, here refers to the CPU, Southbridge chip, various expansion cards, etc.), but when necessary, multiple VC channels can also be bundled together to Corresponds to a memory master device that occupies a particularly large bandwidth. Therefore, VC-SDRAM can also ensure continuous and efficient data transmission when multiple tasks are executed simultaneously. Another feature of VC-SDRAM is that it remains pin compatible with traditional SDRAM. Manufacturers do not need to redesign the motherboard wiring to make the motherboard support it. However, because it is controlled differently from traditional SDRAM, it requires the support of a control chipset before it can be used. Chipsets that currently support VC-SDRAM include VIA's ApolloPro133 series, ApolloMVP4, and SiS's SiS630.