1 System composition
The composition of the table tennis game machine is shown in Figure 1. The game rules stipulate: three wins out of five games; one game at 11 points; the referee sends the start signal of the game, triggering the FPGA internal random number generator module to generate the first serving party; during the game, after the player obtains the right to serve twice in a row, the right to serve is handed over. To the opponent, if the ball is served without the right to serve, the referee's foul audio circuit will sound; 13 LEDs are arranged in a row to simulate a table tennis table; the lit LED simulates a table tennis ball and is controlled by the FPGA to move from left to right or from right to left; Competitors input simulated hitting signals through buttons to control the LED shift direction; if the bright LED moves between the midpoint of the table and the opponent's end point, the opponent fails to press the hitting button in time to cause it to move in the opposite direction. , that is, one point is lost.
2 Functional module design
In Figure 1, the control end designed based on FPGA is the core of the entire system, which mainly consists of a simple random number generator, a serving right controller, a table tennis It is composed of modules such as ball position controller, Party A and Party B scoring controller, and foul sound controller. The entire control end adopts a modular design. Function modules are first written in VHDL language, and then the top-level schematic diagram is used to connect the functional modules. The difficulty of the design lies in coordinating the work of each module and strictly abiding by the timing relationship between each signal. This system uses a 1 kHz system clock.
2.1 Simple random number generator
The right to serve the first ball in the game is determined by the data generated by the random number generator. Its randomness requirements are not strict, so a very simple mode is adopted Generate, that is, once the FPGA is powered on, the system clock frequency will generate a square wave signal square. When the referee closes the start switch to generate the rising edge of the start signal, the square signal value at this time is read as the random number generator output randq. The module simulation is shown in Figure 2, and the results meet the design requirements. This module is designed to ensure that the square signal period should be much larger than the rising edge establishment time of the start signal to ensure the correct reading of random data.
2.2 Serving Right Controller
The control process of the Serving Right Controller is: if the reset button is pressed, the Serving Right digital tube displays 8; otherwise, when the start game switch is closed , displays the value of the random number generator (0 or 1, 0 represents Party A, 1 represents Party B). In the game, in order to comply with the rules of exchange of serving rights, it is designed that when the sum signal sum_sc of the scorers of both sides is not 0 (that is, when the falling edge of the lowest sum_sc0 of the total score arrives), the display of the digital tube of the serving right changes from 0 to 0. is 1 or changes from 1 to 0.
In the design of this module, the signal control of the serving right digital tube is controlled by multiple clocks, that is, the start switch start and the score value sum_sc0 signal. This cannot be realized with one process in the VHDL programming language. The two signals must be combined into one clock signal and the triggering edges of both clocks must be unified. Therefore, the best clock triggering method is the fqq_en signal as shown in Figure 3. In order to meet this timing requirement, the entity sum_sc_mod2 is designed with the help of the second-lowest sum_sc1 signal of the score sum. Since the frequencies of start and sum_sc1 are far lower than the system clock signal clk frequency, the clk high-frequency signal can be used to capture its edge to generate a new clock signal. fqq_en, and generate its count value, the simulation waveform is shown in Figure 4(a). In order to ensure that the digital tube display of the serving right is correct, the entitv led_fqq_ctl is designed to generate the corresponding digital tube output signal led_fqq based on its count value when the falling edge of fqq_en occurs. The simulation waveform is shown in Figure 4(b).
The VHDL core program of the serve right controller is as follows:
2.3 Table tennis position control, A and B scoring, foul sound control
Table tennis position control The circuit is the core of the FPGA control end. According to the competition rules, it is implemented using a Mealy-type state machine, which greatly reduces the design difficulty.
The state machine defines 7 states. The definition of each state is shown in Table 1. The state transition is shown in Figure 5. The transition conditions are shown in Table 2. The specific procedures are as follows.
3 Top-level module simulation test
Due to space limitations, the design of common modules such as frequency dividers and decoders in this system will not be described in detail. The final top-level schematic design is As shown in Figure 6, the simulation waveform is shown in Figure 7. Analysis of the waveform shows that after the start of the game signal is generated in the figure, Party B has the right to serve for the first time. Party A's serve causes the foul audio circuit to sound, that is, the speaker signal is high level. , then Party B serves, and the table tennis ball shifts in sequence. After Party A successfully catches the ball, Party B fails to catch the ball successfully. Party A scores, and the cnta signal is "0110000". Note that the output here is the drive digital tube output signal, which represents the number "1 ". Through simulation, it can be seen that the system design meets the requirements of game console competition rules.
4 Conclusion
Using VHDL language programming, a table tennis game console was successfully designed based on FPGA. Through simulation verification, it can be seen that the results meet the design requirements, and the system has serving rights control, Various functions such as automatic scoring and foul prompts can effectively simulate actual table tennis matches. The idea of ??further improving the system is to use human body induction sensors to collect hitting signals, and use FPGA to generate video signals and transmit them to TVs or monitors to more intuitively display the movement trajectory of table tennis, thereby truly realizing human-computer interaction and optimizing virtual effects. .