Chapter 1 Electrostatic Discharge
1.1 Current and Electrostatic Discharge
1.1.1 Current and Electrostatic Discharge
1.1.2 Electrostatic Discharge
1.1.3 Main ESD patents, inventions and innovations
1.1.4 ESD failure mechanism
1.2 Basic concepts of ESD design
1.2 .1 ESD design concepts
1.2.2 Device response to external events
1.2.3 Optional circuit loops
1.2.4 Switches
1.2.5 Decoupling of current paths
1.2.6 Decoupling of feedback loops
1.2.7 Decoupling of power rails
1.2.8 Local and global distribution
1.2.9 Use of parasitic components
1.2.10 Buffering
1.2.11 Ballast
1.2.12 Unused portions of semiconductor devices, circuits or chip functions
1.2.13 Impedance matching between floating and non-floating networks
1.2.14 Non-connected structures
1.2.15 Use of virtual structures and virtual circuits
1.2.16 Non-shrunk source events
1.2.17 Area effectiveness
1.3 Time constant
1.3.1 Electrostatic and magnetostatic time constant
1.3.2 Thermal time constant
1.3.3 Thermal physical time constant
1.3.4 Semiconductor device time constant
1.3.5 Circuit time constant
1.3.6 Chip-level time constant
1.3.7 ESD time constant
1.4 Capacitance, resistance, inductance and ESD
1.4.1 Capacitance
1.4.2 Resistance
1.4.3 Inductance
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1.5 ESD and rules of thumb
1.6 Lumped-distributed analysis and ESD
1.6.1 Current and voltage distribution
1.6.2 Lumped system and distributed system
1.6.3 Distributed system: ladder network analysis
1.6.4 Resistor-inductor-capacitor (RLC) distributed system
1.6.5 Resistor-Capacitor (RC) Distributed System
1.6.6 Resistor-Conductance (RG) Distributed System
1.7 ESD Measurement and Quality Factor
1.7.1 ESD measurement at the chip level
1.7.2 ESD measurement at the circuit level
1.7.3 ESD device measurement
1.7.4 Commercial Measurement of ESD Quality and Reliability
1.8 Twelve-step ESD plan formation method
1.9 Summary of this chapter
Exercises
References
Chapter 2 Design Synthesis
2.1 Structure and synthesis of semiconductor chip ESD protection
2.2 Electrical connection and spatial connection
2.2. 1 Electrical connection
2.2.2 Thermal connection
2.2.3 Spatial connection
2.3 ESD protection, latch-up effect and noise
2.3.1 Noise
2.3.2 Latch-up effect
2.4 Interface circuit and ESD components
2.5 ESD power clamping network
2.6 ESD rail-to-rail devices
2.6.1 Placement of ESD rail-to-rail networks
2.6.2 Peripheral and array I/O
2.7 Protection ring
2.8 Pad, float
Moving pads and non-connected pads
2.9 Structure under the connected pad
2.10 Summary of this chapter
Exercises
References
Chapter 3 ESD Design: MOSFET Circuit Design
3.1 Basic ESD Design Concepts
3.1.1 Channel Length and Line Width Control
3.1.2 ACLV control
3.1.3 MOSFET ESD design example
3.2 ESD MOSFET design: channel width
3.3 ESD MOSFET design: contact hole
3.3.1 Gate to contact hole spacing
3.3.2 Contact hole spacing
3.3.3 End contact
3.3 .4 Contact hole to single finger edge
3.4 ESD MOSFET design: metal distribution
3.4.1 MOSFET metal line design and current distribution
3.4.2 MOSFET Ladder network model
3.4.3 MOSFET wiring: non-parallel current distribution
3.4.4 MOSFET wiring: parallel current distribution
3.5 ESD MOSFET design : Silicide mask template
3.5.1 Silicide mask template design
3.5.2 Silicide mask design across source and drain
3.5.3 Coverage Gate silicide mask design
3.5.4 Silicide and segmentation
3.6 ESD MOSFET design: series ***source*** gate structure
3.6.1 MOSFET with series ***source***gate structure
3.6.2 Complete ***source***gate MOSFET
3.7 ESD MOSFET design: coupling and Interdigital design of ballast technology
3.7.1 MOSFET with gate connected to ground through ballast resistor
3.7.2 MOSFET with ballast resistor connected between gate and soft substrate ground
3.7.3 MOSFET structure of source-gate coupled domino ballast resistor
3.7.4 Interdigital structure of MOSFET source-start gate bootstrap ballast resistor
3.7.5 MOSFET Source Start Gate Bootstrap Interdigital MOSFET Using Diode Resistor Ballast
3.8 ESD MOSFET Design: Closed Drain Design Parameters
3.9 ESD MOSFET Interconnect Ballast Flow Design
3.10 MOSFET Design: Separation of Source and Drain
3.11 Summary of this Chapter
Exercises
References
Chapter 4 ESD Design: Diode Design
4.1 ESD Diode Design: The Basis of ESD
4.1.1 Basic Concepts of ESD Design
4.1.2 ESD diode design: ESD diode working principle
4.2 ESD diode design: anode
4.2.1 p Width effect of anode diffusion
4.2.2 p Anode contact
4.2.3 p Design of edge of anode metal silicide area
4.2.4 Isolation distance between p anode and n cathode
4.2.5 p Edge of anode Effect
4.2.6 Circular and Octagonal ESD Diode Design
4.3 ESD Diode Design: Interconnect Lines
4.3.1 Parallel Wiring Design
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4.3.2 Anti-parallel wiring design
4.3.3 Quantitative tapered parallel and anti-parallel wiring
4.3.4 Continuous tapered anti-parallel and parallel wiring
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4.3.5 Center
Feed vertical (side) wiring design
4.3.6 Uniform metal width vertical (side) design
4.3.7 T-shaped extended vertical (side) wiring
4.3.8 Metal design under the bonding pad
4.4 ESD diode design: polysilicon-defined diode design
4.5 ESD diode structural design: n-well diode design
4.5.1 n-well diode wiring design
4.5.2 n-well contact density
4.5.3 n-well ESD design, guard ring and adjacent structure
4.6 ESD diode design: n /p substrate diode design
4.7 ESD diode design: diode string
4.7.1 ESD design: diode string current - Voltage relationship
4.7.2 Diode string components in multi-I/O environment
4.7.3 Pad integration
4.7.4 ESD design: diode string Design - Darlington Amplifier
4.7.5 ESD Design: Diode String Design - Area Ratio
4.8 ESD Diode Design: Triple Well Diode
4.9 ESD design: BICMOS ESD design
4.9.1 P/n well diode ESD structure with high resistance injection sub-collector
4.9.2 STI using deep trench (DT) isolation structure Defined p/n-well diode
4.9.3 STI-defined p/n-well diode using trench (TI) isolation structure
4.10 Summary of this chapter
Exercises
References
Chapter 5 Silicon-on-Insulator (SOI) ESD Design
5.1 Basic Concepts of SOI ESD
5.2 SOI ESD Design: MOSFET with body contact (T-shaped layout)
5.3 SOI ESD design: SOI lateral diode structure
5.3.1 SOI lateral diode design
5.3 .2 SOI lateral diode perimeter design
5.3.3 SOI lateral diode channel length design
5.3.4 SOI lateral diode p/n-/n diode structure
5.3.5 SOI lateral diode p /p-/n diode structure
5.3.6 SOI lateral diode p /p-/n-/n diode structure
5.3. 7 Gateless SOI lateral p/p-/n-/n diode structure
5.3.8 SOI lateral diode structure and SOI MOSFET halo
5.4 SOI ESD design: buried resistor (BR ) Components
5.5 SOI ESD Design: SOI Dynamic Threshold Voltage MOSFET (DTMOS)
5.6 SOI ESD Design: Dual-Gate (DG) MOSFET
5.7 SOI ESD design: FINFET (non-planar double gate) structure
5.8 SOI ESD design: substrate structure
5.9 SOI ESD design: SOI-to-BULK contact structure
5.10 Summary of this chapter
Exercises
References
Chapter 6 Off-chip Driver (OCD) and ESD
6.1 Off-chip Driver (OCD)
6.1.1 OCD I/O standard and ESD
6.1.2 OCD: ESD design basis
6.1.3 OCD: CMOS non- Symmetrical pull-up/pull-down
6.1.4 OCD: CMOS symmetric pull-up/pull-down
6.1.5 OCD: Gunning connection
Receiver Circuit Logic (GTL)
6.1.6 OCD: High Speed ??Transceiver Logic (HSTL)
6.1.7 OCD: Stub Series Termination Logic (SSTL)
6.2 Off-chip driver: mixed voltage interface
6.3 Off-chip driver self-biased well OCD network
6.3.1 OCD: self-biased well OCD network
6.3.2 ESD protection network of self-biased well OCD network
6.4 Off-chip driver: programmable impedance (PIMP) OCD network
6.4.1 OCD: can Programmed impedance (PIMP) OCD network
6.4.2 ESD input protection network for PIMP OCD
6.5 Off-chip driver: Universal OCD
6.6 Off-chip driver : Gate array OCD design
6.6.1 Gate array OCD ESD design implementation
6.6.2 Gate array OCD design: utilization of unused components
6.6. 3 Gate array OCD design: impedance matching of unused components
6.6.4 OCD ESD design: mostly refers to the power rail on the MOSFET
6.7 Off-chip driver: gate modulation network
p>6.7.1 OCD gate modulation MOSFET ESD network
6.7.2 OCD simplified gate modulation network
6.8 Off-chip drive ESD design: integration of coupling and ballast technology
6.8.1 MOSFET with diode source-started gate bootstrap resistance ballast multi-finger MOSFET
6.8.2 MOSFET source-start gate bootstrap resistor ballast multi-finger MOSFET
6.8.3 Gate-coupled domino effect resistive ballasted MOSFET
6.9 Design of off-chip driver ESD: substrate modulated resistive ballasted MOSFET
6.10 Summary of this chapter
Exercises
References
Chapter 7 Receiver Circuit and ESD
7.1 Receiver Circuit and ESD
7.1.1 Receiver circuit and its receive circuit delay
7.1.2 Receiver circuit performance and ESD load effect
7.2 Receiver circuit and ESD
7.2 .1 Receiver circuit and HBM
7.2.2 Receiver circuit and CDM
7.3 Receiver circuit and its development
7.3.1 With half-pass transmission gate Receiver circuit
7.3.2 Receiver circuit with all-pass transmission gate
7.3.3 Receiver circuit, half-pass transmission gate and holdover network
7.3. 4 Receiver circuit, half-pass transmission gate and improved keeper network
7.4 Receiver circuit of pseudo-zero VT half-pass transmission gate
7.5 Zero-transmission gate receiver circuit
7.6 Bleeder transistor receiving circuit
7.7 Receiver circuit with test function
7.8 Receiver circuit of Schmitt trigger feedback network
7.9 Bipolar Bipolar transistor receiving circuit
7.9.1 Bipolar single-ended receiving circuit
7.9.2 Bipolar differential receiving circuit
7.10 Summary of this chapter
Exercises
References
Chapter 8 SOI ESD Circuit and Design Integration
8.1 SOI ESD Design Integration
8.1 .1 Advantages of SOI ESD design compared to bulk CMOS ESD design
8.1.2 Disadvantages of SOI compared to bulk CMOS in ESD design layout
8.1.3 SOI design layout: T Graphic layout style
8.1.4 SOI design layout
: Mixed voltage interface (MVI) T-shaped layout style
8.2 SOI ESD design: diode design
8.3 SOI ESD diode design: mixed voltage interface (MVI) environment
8.4 SOI ESD network in SOI CPU with aluminum interconnection
8.5 SOI ESD design of copper (Cu) interconnection
8.6 SOI ESD design in gate circuit
p>8.7 SOI and dynamic threshold ESD networks
8.8 SOI technology and various ESD issues
8.9 Summary of this chapter
Exercises
References
Chapter 9 ESD Power Clamps
9.1 ESD Power Clamp Design Guidelines
9.2 ESD Power Clamps: Based on Diodes
9.2.1 ESD power supply clamp: Series diode as core clamp
9.2.2 ESD power clamp: Series diode as core clamp - metal cladding design concept
9.2.3 ESD power supply clamp: Series diode as core clamp - boost design concept
9.2.4 ESD power clamp: Series diode string as core clamp - cantilever design concept
9.2.5 ESD power clamp: triple-well series diode as core clamp
9.2.6 ESD power clamp: SOI series diode ESD power clamp
9.3 ESD power clamp: based on MOSFET
9.3.1 CMOS RC triggered MOSFET ESD power clamp
9.3.2 Mixed voltage interface RC triggered ESD power clamp
9.3.3 Voltage triggered MOSFET ESD power clamp
9.3.4 Improved RC triggered MOSFET ESD power clamp
9.3.5 RC network triggered MOSFET ESD power clamp layout
9.4 ESD power clamp: based on bipolar transistor
9.4.1 Bipolar ESD power clamp: voltage triggered ESD power clamp
9.4.2 Bipolar ESD power supply clamp: Zener breakdown voltage triggers
9.4.3 Bipolar ESD power supply clamp: BVCEO voltage triggers ESD power supply clamps
9.4.4 Bipolar ESD power clamp: Mixed voltage interface forward bias voltage and BVCEO breakdown synthesis
Bipolar ESD power clamp
9.4.5 Bipolar ESD power clamp: ultra-low voltage forward bias voltage trigger
9.4.6 Bipolar ESD power clamp: capacitive trigger
9.5 ESD power clamp: based on Silicon controlled rectifier of rectifier
9.6 Summary of this chapter
Exercises
References