Application publication number: CN 1 13228268A.
ApplicationNo.: CN20 1880 100493.2
Classification number: H0 1L23/538
Classification: basic electrical components
Publication (announcement)No.: CN 1 13228268A
Release date (announcement): 202 1-08-06
Name of invention: chip packaging structure, electronic equipment, chip packaging method and packaging equipment.
Inventor: Guo Mao; Li Wei; zhang xiaodong
Applicant: Huawei Technologies Co., Ltd.
Date of application: 20 18- 12-29
Date of publication of application: 202 18-06
A refers to the trial stage, without authorization.
Combined with the recent introduction of chip engineers, it is speculated that chrysanthemum factory should make great efforts in manufacturing chips. It is not clear whether it includes the manufacturing process or whether manufacturing depends on SMIC.
abstract:
The application provides a chip packaging structure, electronic equipment, a chip packaging method and packaging equipment, which comprise a chip and a substrate, wherein the first surface of the chip is provided with a first electrical connector, and the first surface of the substrate is provided with a first passivation layer with a groove, and a second electrical connector is plated in the groove. The first electrical connector of the chip and the second electrical connector arranged in the first passivation layer are directly electrically connected, and the thickness of the first passivation layer is relatively thin, so that the communication path between the chip and the substrate is effectively reduced, the conductivity between the chip and the PCB board is improved, and the cost of the chip packaging structure is effectively reduced.
China is also an important base for chip packaging and testing. There are four leading enterprises in chip packaging and testing: Changdian Technology, Tongfu Microelectronics, Tianshui Huatian Technology and Fang Jing Technology. Chip manufacturing is divided into three links, namely, upstream design link, midstream manufacturing link and downstream packaging and testing link. Compared with the design and manufacture, the technical difficulty of sealing and testing is relatively low.
Due to the low difficulty of chip packaging test technology, economies of scale will become possible, so the main packaging test enterprises in the world are basically distributed in the densely populated Asia-Pacific region. And driven by the cost and supporting facilities, almost all the packaging and testing enterprises in the world began to set up factories in China, which made the packaging and testing output value of mainland chips grow at a compound annual growth rate of 20%, and the industrial transfer trend was basically determined.
Attached to the integrated circuit industry chain.
Come on, my motherland. Get rid of the bottleneck of chip manufacturing as soon as possible.