The commonly seen memories in order of appearance are: EDO, SD, DDR, DDR2, DDR3.
In fact, there are many types of memory.
According to different components, RAM memory is divided into the following eighteen types:
01.DRAM (Dynamic RAM, dynamic random access memory):
This is the most common RAM. A tube and a capacitor form a bit storage unit. DRAM stores each memory bit as a charge in the bit storage unit, and uses the charge and discharge of the capacitor to perform storage operations. However, because the capacitor itself has There is a leakage problem, so it must be refreshed every few microseconds, otherwise the data will be lost. The access time and discharge time are consistent, about 2~4ms. Because the cost is relatively cheap, it is usually used as the main memory in computers.
02. SRAM (Static RAM, Static Random Access Memory)
Static means that the data in the memory can reside in it without the need to access it at any time. Every 6 electron tubes form a bit storage unit. Because there is no capacitor, it can operate normally without constant charging. Therefore, it can process faster and more stably than ordinary dynamic random processing memory, and is often used as a cache.
03.VRAM (Video RAM, video memory)
Its main function is to output the video data of the graphics card to the digital-to-analog converter, effectively reducing the workload of the graphics display chip . It adopts a dual data port design, one of which is a parallel data output port and the other is a serial data output port. Mostly used for high-end memory in advanced graphics cards.
04.FPM DRAM (Fast Page Mode DRAM, fast page switching mode dynamic random access memory)
Improved version of DRAM, most of which are 72Pin or 30Pin modules. When traditional DRAM accesses data of a BIT, the row address and column address must be sent once each to read and write the data. After FRM DRAM triggers the row address, if the address required by the CPU is in the same row, it can continuously output the column address without outputting the row address. Since the addresses of general programs and data arranged in the memory are continuous, in this case, the required data can be obtained by outputting the row address and then the column address continuously. FPM divides the memory into many Pages, ranging from 512B to several KB. When reading data in a continuous area, the data in each page can be directly read through the fast page switching mode, thus greatly improving the efficiency of the memory. Improve reading speed. Before 1996, in the early days of the 486 era and the PENTIUM era, FPM DRAM was widely used.
05.EDO DRAM (Extended Data Out DRAM, Extended Data Output Dynamic Random Access Memory)
This is a type of memory that appeared after FPM, generally 72Pin, 168Pin module. It does not need to output the row address and column address when accessing each BIT data like FPM DRAM and allow it to stabilize for a period of time before valid data can be read or written. The address of the next BIT must wait for this read and write operation. Output only when completed. Therefore, it can greatly shorten the time waiting for the output address, and its access speed is generally about 15 times faster than the FPM mode. It is generally used in the standard memory of Pentium motherboards below mid-range. Later 486 systems began to support EDO DRAM. By late 1996, EDO DRAM began to be implemented. .
06.BEDO DRAM (Burst Extended Data Out DRAM, Burst Extended Data Output Dynamic Random Access Memory)
This is an improved EDO DRAM, proposed by Micron , which adds an address counter on the chip to keep track of the next address.
It is a burst reading method, that is, after a data address is sent, each of the remaining three data can be read in only one cycle, so multiple sets of data can be accessed at one time, and the speed is faster than EDO DRAM is fast. However, there are very few motherboards that support BEDO DRAM memory. Only a few models provide support (such as VIA APOLLO VP2), so it was quickly replaced by DRAM.
07.MDRAM (Multi-Bank DRAM, multi-slot dynamic random access memory)
A memory specification proposed by MoSys, which is internally divided into several different categories of small A storage bank (BANK) is composed of several independent small unit matrices. Each storage bank is connected to each other at a higher data speed than the external one. It is generally used in high-speed display cards or accelerator cards, and also in a small number of host computers. The board is used in the L2 cache.
08.WRAM (Window RAM, Window Random Access Memory)
The memory mode developed by South Korea's Samsung Company is an improved version of VRAM memory. The difference is its control circuit There are one to twenty groups of input/output controllers, and the data access mode of EDO is adopted, so the speed is relatively fast. It also provides a block moving function (BitBlt), which can be used in professional drawing work.
09. RDRAM (Rambus DRAM, high-frequency dynamic random access memory)
A memory mode independently designed and completed by Rambus Company. The speed can generally reach 500~530MB/s. It is more than 10 times that of DRAM. However, the memory controller needs to make considerable changes after using this memory, so they are generally used in professional graphics acceleration adapter cards or video memory in TV game consoles.
10.SDRAM (Synchronous DRAM, synchronous dynamic random access memory)
This is a memory mode that achieves FSB Clock synchronization with the CPU. Generally, a 168Pin memory module is used. group, the operating voltage is 3.3V. The so-called clock synchronization means that the memory can access data synchronously with the CPU, which can cancel the waiting cycle and reduce the delay of data transmission, thus improving the performance and efficiency of the computer.
11. SGRAM (Synchronous Graphics RAM, Synchronous Graphics Random Access Memory)
An improved version of SDRAM. It uses block, that is, every 32 bits as the basic access unit. Individual It can easily retrieve or modify accessed data, reducing the number of overall memory reads and writes. In addition, a graphics controller has been added for drawing needs, and a block moving function (BitBlt) is provided, which is significantly more efficient than SDRAM.
12.SB SRAM (Synchronous Burst SRAM, synchronous burst static random access memory)
General SRAM is asynchronous. In order to adapt to the increasingly faster speed of the CPU, it is necessary to Make its working clock synchronized with the system, this is the reason why SB SRAM is produced.
13.PB SRAM (Pipeline Burst SRAM, pipeline burst static random access memory)
The rapid increase in CPU FSB speed has put forward higher requirements for the memory that matches it. Requirements, pipeline burst SRAM has become an inevitable choice to replace synchronous burst SRAM, because it can effectively extend the access clock, thereby effectively increasing the access speed.
14.DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory)
As a replacement product of SDRAM, it has two major characteristics: First, it is faster than SDRAM There is a doubled improvement; secondly, DLL (Delay Locked Loop: Delay Locked Loop) is used to provide a data filter signal. This is the current mainstream model in the memory market.
15.SLDRAM (Synchronize Link, Synchronized Link Dynamic Random Access Memory)
This is an extended SDRAM structure memory. While adding more advanced synchronization circuits, The logic control circuit has also been improved, but due to technical indicators, it is difficult to put it into practical use.
16. CDRAM (CACHED DRAM, Synchronous Cache Dynamic Random Access Memory)
This is a patented technology first developed by Mitsubishi Electric Company. It is based on the external pins and external pins of the DRAM chip. An SRAM is inserted between the internal DRAM to be used as a secondary cache. Currently, almost all CPUs are equipped with a level-1 CACHE to improve efficiency. As the CPU clock frequency increases exponentially, the impact of CACHE not being selected on system performance will be greater and greater, and the level-2 CACHE provided by CACHE DRAM will CACHE is used to supplement the deficiencies of the CPU's first-level CACHE, so it can greatly improve CPU efficiency.
17.DDRII (Double Data Rate Synchronous DRAM, second generation synchronous double rate dynamic random access memory)
DDRII is DDR’s original SLDRAM alliance that was disbanded in 1999 Future new standards after integrating existing research and development results with DDR. The detailed specifications of DDRII have not yet been determined.
18.DRDRAM (Direct Rambus DRAM)
It is one of the next generation mainstream memory standards. It was designed and developed by Rambus Company. It connects all pins to a * Different Bus, which can not only reduce the size of the controller, but also increase the efficiency of data transmission.