Overview of HDL (Hardware Description Language)
With the development of EDA technology, it is a trend to design PLD/FPGA with hardware language. At present, the main hardware description languages are VHDL and Verilog HDL. VHDL was developed earlier with strict grammar, while Verilog HDL is a hardware description language developed on the basis of C language with relatively free grammar. Compared with verilog HDL, the writing rules of VHDL are more complicated than verilog, but Verilog's free syntax also makes a few beginners make mistakes easily. Many foreign electronics majors will teach VHDL at undergraduate level and verilog at postgraduate level. From the domestic point of view, there are many reference books in VHDL, and it is easy to find information, while there are relatively few reference books in Verilog HDL, which brings some difficulties to learning Verilog HDL.
Let's introduce Verilog HDL in detail.
Verilog HDL is a component description language developed on the basis of the most widely used C language. Initiated by PhilMoorby of GDA (Gateway Design Automation) Company at the end of 1983. At first, only one simulation verification tool was designed, and then related fault simulation and time sequence analysis tools were developed one after another. 1985, Moorby launched its third commercial simulator Verilog-XL, which was a great success, thus making Verilog HDL rapidly popularized and applied. 1989 CADENCE company acquired GDA company, making VerilogHDL the exclusive patent of this company. 1990 CADENCE company published Verilog HDL publicly, and established LVI organization to promote Verilog HDL to become IEEE standard, namely IEEE standard 1364- 1995.
Verilog HDL is easy to learn and use. If you have programming experience in C language, you can learn and master it quickly in a short time, so you can arrange Verilog HDL content to be taught in ASIC design related courses. Because HDL language itself is specially designed for hardware and system design, this arrangement can enable learners to gain experience in designing actual circuits at the same time. In contrast, learning VHDL is more difficult. However, the free syntax of Verilog HDL can easily lead beginners to make some mistakes, which should be noted.
Choose VHDL or verilog HDL?
This is the most frequently asked question for beginners. In fact, there is not much difference between the two languages, and their descriptive ability is similar. After mastering one of the languages, you can learn another language quickly through short-term study. What language to choose depends mainly on the habits of people around you, which can facilitate future study and communication. Of course, if you are an ASIC designer, you must first master verilog, because in the field of IC design, more than 90% of companies use verilog for IC design. For PLD/FPGA designers, they can choose two languages freely.