The year-end bonuses are usually in May and the year-end bonuses are usually two months, but there are also three to five months. But that proportion is relatively small. Year-end bonuses are usually determined based on overtime hours worked.
Job responsibilities:
1. Develop and maintain block and SoC chip DFT design and implementation.
2. Plan mbist, stuck at, and at speed test plans, and deeply understand the principles of each test plan.
3. Cooperate with STA engineers to solve SDC and timing related issues in test mode.
4. Cooperate with ATE test engineers to solve problems related to mass production testing.
5. Complete ATPG verification independently.
Qualifications:
1. Master's degree or above in electronics, communications or computer or other related majors.
2. Have more than 2 years of DFT work experience; familiar with ASIC design.
3. Proficient in using Synopsys or Mentor DFT tools.
4. Proficiency in using Perl (Python), Tcl and Shell scripts is preferred.
5. Applicants with relevant experience in 28nm and below process ASIC processes will be given priority.
6. Priority will be given to those with experience in repair and mass production.