The South Bridge chip is responsible for the communication among I/O buses such as PCI bus, USB, LAN, ATA, SATA, audio controller, keyboard controller, real-time clock controller and advanced power management. The North Bridge is responsible for the data exchange between CPU and memory and graphics card, while the South Bridge is responsible for the data exchange between CPU and PCI bus and external devices.
North-South Bridge is a very popular motherboard chipset architecture with a long history. There are two large-area chips on the main board of the north-south bridge structure. Northbridge chip near CPU is mainly responsible for controlling the data exchange between AGP graphics card, memory and CPU. Near the PCI slot is the south bridge chip, which is mainly responsible for data exchange of floppy drive, hard disk, keyboard and add-on card. The traditional north-south bridge architecture is connected by PCI bus. The commonly used PCI bus has a working frequency of 33.3MHz and a transmission width of 32bit, so the theoretical maximum data transmission rate is only 133MB/s/s ... Due to the enjoyment of PCI bus, the low data transmission rate between the north and south bridges of the motherboard has gradually become a bottleneck affecting the overall performance of the system when the transmission rate of subsystems and other peripheral devices continues to increase. Therefore, from Intel i8 10, chipset manufacturers began to seek a solution that can increase the bandwidth of the North-South Bridge connection.
Intel: AHA Acceleration Center Architecture Intel's Acceleration Center Architecture (AHA) first appeared in its famous integrated chipset i8 10. In the i8 10 chipset, Intel changed the classic north-south bridge architecture and adopted a brand-new acceleration center architecture. The architecture of acceleration center consists of GMCH (Graphics &; It is equivalent to the memory controller Hub (graphics/memory control center) and ICH(I/O controller Hub) of the traditional Southbridge chip, and the newly added FWH (firmware Hub, equivalent to the BIOS ROM in the traditional architecture) * * * 3 chip.
In this new acceleration center architecture, the two chips are not connected by PCI bus, but by a dedicated bus, which can provide twice the bandwidth of PCI bus. In this way, every device including PCI bus can communicate directly with CPU, and the memory controller and graphics controller in Intel 8 10 chipset can also use 8-8 bit133 MHz "2× mode" bus, which makes the data bandwidth reach 266MB/s, and most of its subsequent i8xx chipsets also adopt this architecture.
In fact, this system is not much different from the South-North Bridge structure. It mainly separates the PCI control part from the North Bridge (the North Bridge becomes GMCH), and the ICH is responsible for PCI and other functions that were previously handled by the South Bridge. ICH also adopts the acceleration center architecture to establish direct connection between the graphics card and memory and the integrated AC'97 controller, IDE controller, dual USB ports and PCI add-in cards. Because Intel Center architecture provides PCI bandwidth of 266 MB per second, more and more information can be transmitted between I/O controller and memory controller. Coupled with the optimization of arbitration rules, the system can run more threads at the same time, thus achieving more obvious performance improvement. The transmission rate between GMCH and ICH reaches 8 bits 133MHz DDR (equivalent to 266MHz and 266MB/s), which greatly improves the bandwidth between PCI bus, USB bus and IDE channel and system memory and processor.
Of course, because there is only one channel between two HUBs, only one device can transmit data at a time, including devices on PCI bus, and the maximum data transmission rate of devices on PCI bus is still 133MB/s/s, so to some extent, Intel's current solution is not perfect. Therefore, Intel is also looking for a new solution, which is 3G IO (Third Generation Input/Output) technology. 3GIO, also known as Arahahoe and serial PCI technology, is a future technology developed by Intel, which provides high-bandwidth and high-speed connections between computer subsystems and I/O peripherals.
VIA: V-Link Bridging Technology VIA has also introduced V-Link technology with similar performance. This technology first appeared in its DDR chipset through Apollo Pro266. Architecturally, Pro266 still follows the traditional north-south bridge structure, consisting of VT8633 North Bridge and VT8233 South Bridge. However, different from the previous architecture, VIA abandoned the traditional PCI bus and used its own V-Link acceleration center architecture in the communication between the North and South Bridges. In the V-Link architecture, PCI bus becomes the downstream of the south bridge and becomes an equal connection with IDE channel, AC'97 Link, USB and I/O.
The V-Link bus is still a PCI-style 32-bit bus, but its working frequency has increased from 33MHz to 66MHz, so the bandwidth between the north and south bridges has increased to 266MHz, which can be said to double the bandwidth of the traditional PCI bus 133MHz. In the past, most of the bandwidth of PCI bus was occupied by IDE devices, and the communication speed between the north and south bridges could not be guaranteed, which affected the performance of the system to some extent, especially when the IDE transmission task was heavy. V-Link technology separates the communication between the north and south bridges from the busy PCI bus, which effectively ensures the fast and complete information transfer inside the chipset and helps to improve the system performance. In the future development plan, VIA intends to further increase the frequency of V-Link to 133MHz, and double its bandwidth to 533MHz.
In addition to the above-mentioned bandwidth enhancement technology, VIA also designed the latest generation of architecture standard-HDI (High Bandwidth Differential Interconnection Technology). HDIT structure provides a cost-effective and flexible chip baseline design platform for the majority of system OEMs. In today's mainstream desktop and mobile PC design, HDI allows some advanced technical specifications and standards, such as DDR 266 memory interface, AGP 4×, 533MB/s V-Link bus to be combined with highly integrated HDI South Bridge chip. In the design of workstations and servers that need great flexibility, by setting the working mode of HDIT, the best effect of memory interface and AGP port configuration in HDIT North Bridge chip can be achieved, and the memory data bandwidth can be doubled or even quadrupled, and the maximum bandwidth can reach 4.2 GB/s.
SiS:MuTIOL architecture Multi-thread I/O Link (MuTIOL for short) architecture of silicon system first appeared in its SiS635 chipset. Although the silicon series regards it as a single chip structure, there is still a "north-south" division inside SiS635. In SiS630s and before, PCI bus was also used as the data channel of north-south connection, and in order to solve the bandwidth problem, multi-thread I/O Link architecture was introduced into the silicon system. As can be seen from its architecture diagram, multithreaded I/O Link is responsible for data transmission of eight devices, namely: PCI bus (all devices above are one device of multithreaded I/O Link), first IDE channel, second IDE channel, first USB channel, second USB channel, AC'97 audio, V.90 soft modem and media access controller (MAC). Specifically, multithreaded I/O Link is actually eight independent data pipelines, each with a working frequency of 33.3MHz and a bit width of 32 bits for data transmission. Such a pipeline is equivalent to the bandwidth of a 32-bit PCI bus 133MB/s, and eight pipelines add up to 1.2GB/s, which is why the bandwidth can exceed 65438. Compared with Intel and VIA's Link channel, the total bandwidth is obviously improved, but it is not as good as 266MB/s per pipeline of Link channel, that is to say, the maximum transmission rate of each device is still limited to 133MB/s. Other devices are low-speed devices except IDE, and the exclusive bandwidth of133 MB/s is of little significance to them.
However, the discrete channel design also has its disadvantages. The reason why PCI bus and Hub Link or V-Link channel only allow one device to transmit data at a time is because there is only one line and the frequency used for transmission is fixed. If a separate channel is adopted, this problem can be solved well. Although on the memory side of DMA, only one device can be served at a time, the next device can be served immediately without waiting for the bus to be cleared, while the data requests of other devices (one or more) can be sent to the memory control side without disturbing the work of the current devices (I believe these eight devices will have queue registers to sort tasks), and the next task can be executed immediately after data transmission. From this point of view, the design of multi-thread I/O link is beneficial to multi-task operation.
AMD:HyperTransport Bus On the issue of how to connect the North-South Bridge chip and make the IDE disk performance fully play, AMD has also developed a transmission interface that can be applied to various high-speed chipsets. This is LDT (Lightning Data Transmission), which was renamed HyperTransport in February 2006, 5438+0. HyperTransport technology was first announced by AMD in April this year, and it was supported by many famous manufacturers including NVIDIA and Ali. This technology aims to improve the data transmission rate of various IC chips (including PC, PDA and many other aspects). At present, its bandwidth has reached 12.8GB/s, and the transmission speed is more than 96 times that of the existing PCI technology.
HyperTransport consists of two point-to-point unidirectional data transmission paths (one for input and one for output). The data bandwidth of the two unidirectional transmission paths can be flexibly changed according to the data size, with a minimum of 2 bits, which can be adjusted to 4 bits, 8 bits, 16 bits and 32 bits. HyperTransport runs at a clock frequency of 400MHz, but it uses the same double clock frequency trigger technology as DDR, so the data transmission rate can reach 800MB/s at the rated frequency of 400MHz. However, another major feature of HyperTransport is that when the data width is not 32 bits (4 bytes), it can also achieve the effect of batch transmission of data in 32 bits (4 bytes). For example, 16bit data is transmitted in two batches, and when 8 bits data is used, it is transmitted in four batches. This method of subcontracting data transmission gives HyperTransport more flexibility, with a minimum of 4 bytes and a maximum of 64 bytes. It greatly improves the rapid transmission of data and improves the data processing performance of the system.
HyperTransport can not only transmit data between chips at high speed, but also has the characteristics of "packet-based", "two unidirectional data streams and point-to-point data connection" and "elastic data bandwidth". Using HyperTransport bus can improve the bottleneck of system data transmission, provide a basis for system designers to manufacture more efficient system equipment, and really speed up the operation efficiency of the whole system.
The first application of HyperTransport technology on chipset appeared on NVIDIA's first system chipset nForce. NForce chipset consists of Northbridge Integrated Graphics Processor (IGP) and Southbridge Media and Communication Processor (MCP). For NVIDIA's nForce chipset system, HyperTransport bus is used to connect MCP, IGP and CPU. Between the North Bridge and the South Bridge, nForce obtains a huge data bandwidth of 800MB/s between IGP and MCP through a synchronous 8-bit high-speed data bus without adding more pins. Although it is lower than the multi-threaded I/O Link architecture of silicon system in numerical value, because HyperTransport has the technical characteristics of two unidirectional data streams, its bandwidth gain is also quite significant, and it is believed that it can meet the needs of peripherals in at least two or three years.