Date: 2019-09-2810: 40: 32
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Typora-copy-images-to:。 /Introduction to Computer System-Notes
This chapter is a general explanation of some basic knowledge of computers, as well as the profound philosophical thoughts that computers can produce and the levels of computer composition.
Take an 8-bit binary as an example, here we need to consider whether the binary is positive or negative. If it is a negative number, we need to get the complement to calculate, and the highest bit in the complement representation represents the sign bit.
Decimal to binary is to divide by 2 at a time, record the remainder, and then arrange it from right to left to get the binary number.
These four structures are the basic structures of Boolean algebra and the fixed gate structures of many electronic devices.
Floating-point numbers are used to represent decimals, but they are not absolutely accurate. They can only be as close to the result as possible within the range of binary numbers. Floating-point numbers are expressed by their inherent structures, which are similar to scientific counting methods and consist of three parts, such as12340 =1.234 *104.
Sign bit: 1bit 0 is a positive number; 1bit0 is a negative number.
Numerical range: 8-bit exponential part
Numerical precision: 23-bit mantissa part
Every four bits of binary can correspond to a binary of 16, so the direct conversion between four bits and four bits is enough.
? For example, 001111kloc-0/110 is converted into 3 D 6 E.
Similarly, converting hexadecimal to binary means converting each bit into four binary 0 1.
This chapter introduces some common binary transformations, in fact, the most important one is complement, which simplifies the realization of computer by converting subtraction into addition, while floating-point numbers expand the range of values by sacrificing the precision of numbers, including representing larger numbers such as 1.5 10 20 and smaller decimals.1.5 *1.
Voltage input in, p disconnects N Unicom, and out and ov practice each other. The output is 0v.
When there is no voltage in, P is on, N is off, out is connected to 2.9V, and the output is 2.9V..
The input of the circuit in and the output of the circuit out are always opposite.
If there is voltage at both ends of A and B, the upper P is turned off and the lower 0v is turned on, then the C output is 0V.
When A and B have no voltage, connect 2.9V to C, and C outputs 2.9V..
? Or gate is the antonym of nor gate, or the antonym of or gate is nor gate.
? The circuit is the output structure of NOR gate, plus the previous NOR gate, the result is reversed.
If any of the left parts. If AB is 0, there will be a connection between the above two P-types, resulting in the output of C being 1, which will be 0 after passing through the NOT gate.
When A and B are both 1, the upper two P lines are both ports, at this time, the C output is 0, and after passing through the NOT gate, it is 1.
At this point, the AND/NOR of binary operation can be realized by circuit. As the most basic element, AND/NOR and XOR can form more complex logic after complex combination. These gates are abstracted by symbols, in which NAND gate and NOR gate are negation of AND gate and OR gate.
Decision unit is a circuit combination that can't store data, and its output depends on the current input. Output data cannot be stored in the decision unit.
Simply put, the decision-making unit generates real-time output from real-time input without saving the result.
Only one of all output results is 1, and all others are zero. These structures are used to detect and match different input patterns, because it can judge the source of input by the output results.
The small circle in front of the AND gate indicates the inversion of the input. Each combination of AB corresponds to one output line. This is a kind of judgment logic.
This is a combination of one dismantling and more.
ABCD has always been the source of input data. If there is voltage, through the combination of two lines of S, it is decided which input is passed to the output by ABCD.
This is an all-in-one combination
Accumulators are used for binary addition. Binary addition is actually the result of three inputs producing two outputs.
For example, A = 10 1 1 plus b =11is actually the gradual addition of each bit of two numbers. But adding two digits here may produce carry, so it should be changed to each and the previous digit of A and B. Supplement. The result also includes the sum of the current bits and a carry. Carryi represents the carry generated by bit i- 1, carryi+ 1 represents the carry generated by bit I, and si is the result of adding the current bits. The truth table is as follows.
The gate circuit is as follows, as you can see. Adding two 1 bits requires so many circuits, and then the generated transmission ci+ 1 will be used as the input carry of the next bit addition.
On the combination of multiple full adders with 1 bit to form most adders.
The rightmost 0 is the carry of the first addition, and then the generated c 1 is the carry of the second addition. S0, S 1, S2 and S3 are the results of each addition, and the final output binary format is C4S3S2S 1S0.
It means that any logical function can be realized through various combinations of AND or NOT gates, which is similar to the three things of Taoism.
The storage unit is used to store the data in the circuit and output it when in use.
Can store 1 bit information, and S and R are two input terminals ab and output terminals. This device stipulates that RS cannot be zero at the same time. And this circuit is the same as A and B at any time.
The rule of this device is that when both S and R are 0 or 1, the state of a b is stable.
When r is from1->; 0，a-& gt； 0b-& gt； 1
When s is from1->; 0 is, a->; 1，b->0.
And r or s is from 0->; At 1, the states of A and B are stable.
So only r or s is from1->; 0, the state of ab will change, otherwise ab will remain unchanged, indicating that this device provides the function of saving state and changing state, which is a memory.
Two controls are added in front of the latch, we means writable, d means input data, and when we is 0, SR is 1. Output unchanged, only when w0->; 1, not considered
Whether d is 0 or 1. Both of them cause one RS to be subordinate to1->; 0, one of the outputs will become 1.
For example, We is 1, and if d is 0, r is1->; 0, b becomes 1a, 0 We becomes 1. If d is 1, s will be1->; 0, then a becomes 1b becomes 0.
So when We is 1, the result of A is synchronized with D, that is to say, the data of D is saved in A, and when we is 0, the data of A will not change.
At this time, this latch can be changed by data D and read-write control W to save data.
A multi-bit register is formed by connecting a plurality of gated D latches and controlling them with the same WE signal.
The following figure shows a 4-bit register, D is the data source Q and the output storage result. We uniformly control the four-bit latch to write data at the same time.
Memory consists of a large number of storage spaces, and each storage space can hold one data. And each data can be composed of 8-bit or 4-bit or 16-bit latches. Here, the identifier of each storage space is called the address, and the number of latches (that is, the number of bits that can be stored) contained in each data is called the addressing ability. The total number of addresses is called addressing space.
Take SMS as an example. A mobile phone has at most 2000 short messages, and 2000 short messages are called addressing space. Each short message can contain 100 words, that is, the addressing ability is 100.
For example, a computer has 16MB memory, which means that the system has 16M addresses (the addressing space is 16M), and the addressing capacity of each address is 1 byte (the addressing capacity is 8 bits).
In the above, the decision unit does not save data, and the current output depends on the current input. The storage unit is error report data and can be used permanently. Sequential circuit is a combination of decision-making unit and storage unit, which can store both data and data.
Sequential circuits are mainly used to realize finite state machines. The so-called wired state machine means that it has several fixed States and then fixes the input and output. He will switch between these states and enter different states himself. Each state will jump to the next state according to the current state and current input. Like traffic lights. When the input time changes, the red light will jump to the green light, and the green light will jump to the yellow light according to the current red light state.
The finite state machine represents a logically continuous execution process. It is triggered by a local circuit with a fixed frequency.
This chapter mainly talks about the most basic NAND gate devices, and then these devices constitute the most important decision-making unit and storage unit in the computer. These two parts are the core components of the computer. Here, we find that computers actually package and combine some devices, then form control logic, and then slowly evolve programs and data.
At present, the commonly used memory is 2×28×8-8 bit mode, that is, the addressing space is 2×28(2×28 memory cells) and the addressing capacity is 8 (each cell capacity is 8 bits).
To access the memory, it is necessary to obtain the address of a storage unit and put it in the memory address register (MAR) of cpu, and then send a read-write signal to connect the memory with the data register of CPU, and the data will enter the data register (MDR) from the memory.
ALU is an arithmetic and logic operation unit, which can perform addition, subtraction and AND NOR operations. The data length that ALU can handle is word length, which is usually 32-bit and 64-bit word length at present.
Usually ALU is equipped with a small amount of memory to store the intermediate results of calculation. Because reading from memory is too slow, these memories are called registers, and word length and ALU are always
Input and output reading and writing are slow, so a cache is usually allocated, and the CPU and cache exchange data.
The control unit directs other units to work together. The two most important registers are instruction registers, which are used to store the executed instruction, the programmer and the address of the next instruction to be executed. The control unit includes a finite state machine for controlling activities in the system.
Instruction cycle refers to the execution steps of instructions, which are executed step by step under the control of computer control unit. Each instruction is divided into six steps, called beat, and the complete execution process of an instruction is called instruction cycle.
Fetching instructions means loading the instructions in the memory into the instruction register IR of the control unit. PC is the address of the next instruction to be executed. The specific steps are as follows.
Thus, the CPU processes the memory through MAR and MDR registers. MAR keeps the address of a storage unit from which MDR obtains data. The IR register always holds the contents of the instruction to be executed, and the IP always points to the address of the next instruction to be executed.
Each step here requires one or more clock cycles.
Decoding operation is to analyze and check the types of instructions and determine the corresponding operation. Here, the decoder logic device in the third chapter is used to determine the circuit corresponding to the instruction.
If there is an address operation when the instruction is executed, it is executed within this beat, that is, the complete address in the instruction operand is obtained.
To read the actual content corresponding to the operand address, you need to use MAR to load the address calculated in the previous step, and then read the data on the address through MDR.
The instruction has been recognized and the contents of the operand have been obtained. This step is to execute the instruction.
This is the last beat of the instruction cycle, and the result of the previous beat will be written into the target register. After the beat is completed, the control unit will execute the next instruction cycle again from the instruction fetch (because the PC register has pointed to the address of the next instruction to be executed). The following is the sequence switching of the finite state machine in different states.
If we want to change the execution order of instructions, such as jumping to an instruction we want him to execute, we need to jump forward when looping. We should change the address of the instruction executed by the Pc to the address of the instruction we want to execute after the instruction fetch beat of the current instruction and before the instruction fetch beat of the next instruction is executed. This requires the use of control instructions, that is, execution at the above execution beat, and actively modify the contents of pc registers. Then, after this instruction is executed, the PC will take out what we want.
Because CPU is an instruction and an instruction is always executed, such as sum, because instructions run according to the clock cycle of CPU. It means that the clock keeps sending signals to remind the instructions to execute different beats, and then continue to execute the instructions. Therefore, if you want to stop the instruction execution, you must stop the clock. That is, the output of the running control bit is 0, so you stop the clock.
This chapter introduces von Neumann's model. Today's computers are all designed and assembled in this mode. For CPU, different hardware needs to read data into registers, and CPU reads from registers, because the frequency of CPU is much higher than that of memory and io units.
Next, there are six stages of instruction execution. It is a finite state machine. Perform six beats in sequence. Here, the decoder device in the previous chapter is used.
Lc-3 is a simplified version of this computer. Used to understand the complete structure of the whole computer.
? The addressing space is 2 16 (data block) and the addressing ability is 16 bits (data block size). We call this addressing ability of 16 bits "word".
? Memory and frequency are much lower than CPU. Reading data directly from memory by CPU will waste many clock cycles. So there are many registers in the CPU, which actually tell the memory. They can store data like the principle of memory, and only one means that they can be addressed independently. R0...R7 represents eight registers.
? Instruction set includes operation code (what to do)+operand (who to operate). In fact, operands also include addressing methods, that is, how to locate the specific position of operands. This instruction means adding the values of R0 and R2, and the result is saved in R 1.
? Opcodes are mainly divided into three categories: operation, data movement and control. Operation instructions are responsible for processing information (addition, subtraction, multiplication, division and inversion). The data movement instruction is responsible for transferring information between the kernel and registers and between memory/registers and io devices. Control is responsible for changing the execution order of instructions, such as instruction jump.
? All instructions are as follows: DR is the destination register, and the destination register sr is the source register. Usually, the instruction is to transfer the data of SR to Dr.
? Is the way to specify the position of the bit operand. Operands are usually located in three places, memory, registers or data itself. The specific address of the operand is determined by the addressing mode and the matching of the operand. There are five addressing methods, namely immediate number, register, relative addressing, indirect addressing and base address offset.
? There are three one-bit registers N Z P in lc-3. When data is written in any register, according to the result, if the writing result is negative, then n is 1. If the result is 0, z is 1, and if it is written as positive, p is 1. These three registers can provide information for control instructions for conditional branch.
The source operand is bitwise inverted, and the target operand is placed in register addressing mode, that is, both the source operand and the target operand are registers.
The value in the R5 register is bitwise inverted, and the result is put into the R3 register.
Addition is the complement addition of two operands, and it is the bitwise AND of two operands. This instruction requires two source operands and one target operand. Here, one source operand is in register addressing mode, and the other can be in immediate addressing mode or register mode.
Immediate number is to put the value directly in the instruction as the source operand. For example, MOV AL, 0FH transfers the 8-bit immediate number 0FH to the AL register, and 0FH is the immediate number.
The figure below shows the result of adding R5 and R4. It is stored in R 1
Move instructions are instructions to transfer data between registers and memory/registers and Io. Data from memory to register is called loading, and from register to memory is called storage.
If bit [9- 1 1] is DR, it means that the data in the address generation bit is loaded into the modified DR..
If bit [9- 1 1] is SR, data representing this SR is stored in the memory of the address generation bit.
? LD load instruction ST store instruction
? In this mode, bits [0-8] indicate relative displacement. Compared with the displacement of the current pc counter (as mentioned above, the pc counter stores the address of the next instruction to be executed). The limitation of pc relative addressing is that the offset is the address of PC, so the range of offset is limited.
As shown in the figure below, at this time, the value of pc is x40 19, which is x 1AF away from x40 19, and LD and LD are load instructions, which means to save the data in the (x40 19+x 1AF) address to R2.
? LDI load instruction STI store instruction
? In indirect addressing, the address generation bit stores an offset address A, and the value obtained by adding A and PC is another address B, and the value of address B is the final memory address to be operated. Indirect addressing can make instructions jump in a wider range. This is a secondary addressing. X.
? The following figure shows that the current value of pc is x4a1c. Then the offset address a = (x4a1c+x1cc) = x4be8. The picture below is wrong. The content of X4Be8 should be x2 1 10, and then it was changed to X2 1658.
To sum up, do a pc relative addressing first, and then give the value in the obtained address to R3.
? LDR load instruction string store instruction
? This mode first specifies a base address register and then an offset address. The last operand address consists of the value of the base address register+the offset address.
? The following figure shows that the operand address = R2+x1d = x2345+x1d = x 2362, and the contents in the address of x2362 are being loaded into R 1.
? LEA adds the immediate number to the pc counter address and stores it in another register. This command is used to initialize the register.
? Count at once. The naming meaning of this word means that the operand is in the instruction and can be read directly (in text -3). It was obtained immediately. In the above figure, in the instruction reading stage, pc plus 1 becomes x40 19, x40 19-3 =x40 16. ..
? Control instructions can change the execution order of instructions. Needless to say, it must modify the value of the pc counter. Moreover, the control instruction must judge the jump according to the condition. Therefore, the three one-bit registers of NZP mentioned above are also used.
? There are five control instructions in lc-3, conditional jump, unconditional jump and subroutine (function). Trap, interrupt return.
? N is negative, z is zero, and p is positive.
? This condition will be triggered if the value in bit [9- 1 1] matches the NZP three-bit register. The pc counter will calculate the value of pc counter +pc offset, that is, the instruction will jump.
At the execution beat of the instruction cycle, the processor detects the match between the condition code of bit [9- 1 1] and the three-bit register of NZP, and if it matches, modifies the value of the pc counter to complete the instruction jump.
In the above figure, pc = x4028; the modified PC = x4028+x0d9 = x 4101.
If the bit [9- 1 1] of an instruction is set to 1, it will definitely trigger a jump. This jump instruction is called an unconditional jump instruction.
The problem with conditional jump instructions is that the jump is based on the pc offset value. A ***8 bits, the jump range is limited. However, if you want to jump a wider range of instructions in memory, you need to use jump.
Jump instruction. Use the contents of the source operand as the address of the jump, as shown below. Indicates the address to jump to the contents of register R2.
Trap instructions are similar to jump instructions. They all change the contents of the pc counter and jump to the new instruction execution address. But the jump jumps in this program, and the trap is under the control of the linear operating system, that is, jumping to an instruction address of the operating system. This is equivalent to opening the calling system service api. After the execution is completed, the pc counter will be restored to the next address of the trap instruction in the original program, and then the logic of this program will be executed.
Review the lc-3 structure above, and introduce it below.
The global bus of lc-3, which is the thickest and blackest in the figure, has 16 bits, which means that at most 16 bits of information can be transmitted between different structures at a time. At the same time, the bus only allows one data sender to send data.
The steps to access the memory are: first load the address of the memory to be accessed into the MAR register, and then see whether it is a read instruction or a write instruction. If it is LOAD, send RD signal and send the data in the memory to MDR register; If it is a store, the data will be put into the MDR register, and then the WE signal will be sent to save the data in the MDR register to the address specified in the MAR register. (I feel that this is the execution logic of hardware. It is the communication of circuits between devices. )
ALU is an arithmetic logic unit that performs basic operations. It accepts two inputs, one is a register and the other is a register or an immediate number. After ALU calculation is completed, the result will be saved in a general register, and the three condition code registers NPZ will be changed at the same time.
? The pc counter records the next operation to be performed. At the end of the instruction cycle, it increments itself to point to the address of the next instruction. But at the same time, asking the introduced control instruction will also change the value of pc counter. So with PCMUX, PCMUX is a multiplexer (multiple input data, 1 output data), and the input of PCMUX includes PC+ 1.
? MARMUX is used to select the appropriate address input during the execution of load, store and trap instructions. It will select the appropriate address from several input addresses according to the operation code of the instruction. My understanding is that he has dealt with various addressing methods.
? The IR register holds the instruction currently to be executed. When an instruction is executed, it is first taken out of memory and put into MDR, and then transmitted to IR.
? Specifically, it is directly recorded that the beginning of this instruction is 0 1 10, and the corresponding instruction format is as follows, which means that the data at the address of baseR +offset6 is taken out and stored in DR =M[BaseR+offset6].
? This chapter mainly decomposes the basic structure of LC-3 computer, including memory, register, instruction set, addressing mode and condition code ... Although there are several types of registers, they are essentially storage elements for accessing data, only storing different information. Instructions are divided into operation instructions (used to calculate data), data moving instructions (used to move data) and control instructions (used to control instruction jump), which are matched with the three-bit register NPZ.
? Then there are six beats in an instruction execution cycle. Each beat requires one or more constant periods. And the calculation book keeps running according to the signal frequency of the clock cycle. Just understand and remember what different beats do. This is the rule.
? As for instructions, in fact, the operation code is the main one. In this episode, some opcodes have several changes according to different addressing methods, which is actually easy to understand.
? The addressing method is to obtain the data in different positions in the register to varying degrees, which can also be recorded directly. It's not difficult.
? For registers, the summary is that MAR records the address of the memory and MDR saves the value of the memory. The PC points to the next instruction address IR and saves the instruction to be executed.
ZNP records the result of register data change for logical judgment.
Assembly language is another way to express machine instructions. Machines don't understand assembly language. Assembly language will eventually be translated into machine instructions. However, the formats of assembly language and machine instructions are somewhat similar. Each assembly language usually corresponds to a machine instruction. Assembly language needs to be assembled into machine language by assembler.
Label opcode operand; comment
? This is the same as the previous machine instruction. The opcode determines what to do. Operands determine who will do it. There are also different addressing methods here.
? Ru plus R 1, R3, #- 1 plus R3 and-1. The result is stored in R 1, which is an immediate addressing method.
? A symbolic name that points to a storage unit. Can be used directly in memory. It is used for jumping or loading/storing. In fact, it is a simple representation of an address. The following brp jumps to the marked place again.
? Used for labeling; Separated, the computer won't recognize it. It's for people to see.
? Pseudo-operation will not be executed, it is the information that the programmer passes to the assembler. Used to guide the assembler's assembly operation. When the assembler sees this information, it will discard it.
? Tell the assembler where to put the lc-3 program in memory, as shown in origx3050.