1, with the switch button to represent the pulse, each pulse represents 100m, 10 pulse 1km, 1.4 yuan every kilometer, which can display the mileage and expenses synchronously;
2. If it is less than 2km, it will be charged according to 5 yuan; if it is more than 2km, the total cost = starting cost+(mileage -2km) * mileage unit price+.
Waiting time * unit price after waiting;
3. If the waiting time exceeds 2 minutes, it will be charged at 1.3 yuan per minute;
4. You can set the starting price and mileage unit price.
I. Design principles and technical methods:
Including: circuit working principle analysis and schematic diagram, component selection and parameter calculation, circuit debugging method and result explanation;
Software design specification and flow chart, software source code, software debugging method and operation result description.
According to the design requirements, the system inputs signal clk, pricing start signal START, waiting signal stop and mileage pulse signal fin. System output signals include: total cost C0-C3, driving distance K0-K 1, waiting time M0-M 1, etc. The system has two pulse input signals, clk_750k and FIN, in which CLK _ 750K will be divided into 14hz, 15hz and 1hz according to the design requirements, which will be used as the pulse for kilometer charging and overtime charging respectively. Two control input switches start and stop; ; The control process is as follows: start is used as a switch to start charging. When start is high, the system starts charging according to the input. When a passenger gets on the bus and starts driving, the fin pulse is used to charge the car, and the stop at this time needs to be set to 0; If you need to stop and wait, turn stop to high level.
And remove the fin input pulse to wait for charging; When passengers get off the bus and don't wait, directly set start to 0, and the system stops working; Prices began to be classified as starting prices in 5.0 yuan.
The whole design consists of five parts: frequency division module, metering module, charging module, control module and display module.
The metering module is an important part of the whole system, which realizes mileage counting and time counting. The control module is an optional component to realize different charging modes. According to the designed enabling terminal, choose whether to charge by mileage or by waiting time. At the same time, the frequency division module is designed to generate pulse signals with different frequencies to realize the charging of the system. The metering module adopts the driving signal of 1hz, and the charging module adopts the driving signals of 1.4 Hz and 1.3 Hz; Every time the metering module counts, the metering module will count 14 times or 13 times, that is, timing 1.3 yuan/min and logging 1.4 yuan/km. The composition block diagram is as follows:
1. Decimal module:
In order to realize the drive signal of 100m pulse, its composition block diagram is shown in Figure 3:
Figure 3 Block diagram of decimal module
The source program is as follows:
Library ieee
Use IEEE.std _ logic _1164.all;
Use IEEE.std _ logic _ unsigned.all;
Entity Bai Jinzhi is
Port (start, clk2: in std_logic; -Second pulse
A: out std_logic_vector(3 minus 0));
White gold branch;
Platinum building rt 1 is
Signal count _1:STD _ logic _ vector (3downto0);
begin
a & lt= count _ 1；
Process (Start, Clock 2)
begin
If(start='0') and then
count _ 1 & lt； ="0000";
Elsif(clk2' event and clk2=' 1') then
If (count _1= "011"), then
count _ 1 & lt； ="0000";
other
count _ 1 & lt； = count _ 1+' 1 '；
End if;
End if;
End the process;
End rt 1
2. Charging module
; Realize the charging of mileage and waiting time and output it to the display. The component block diagram is as follows:
Fig. 4 Block diagram of billing module
The source program is as follows:
Library IEEE
Use IEEE.std _ logic _1164.all;
Use IEEE.std _ logic _ arith.all;
Use IEEE.std _ logic _ unsigned.all;
Qi Fei is an entity
Port (clk2: in std_logic; -Charging drive signal
Start: in std_logic; -billing start signal
c0，c 1，c2，C3:buffer STD _ logic _ vector(3 down to 0))；
Duan jifei;
Qi Fei's architecture rt 1 Yes.
begin
Process (clk2, start)
begin
If start='0', then C3 < = "0000"; c2 & lt="0000"; c 1 & lt； ="0 10 1"; c0 & lt="0000"; -Starting price 5 yuan.
Elsif clk2' event, and clk2=' 1'
If c0=" 100 1 ",then C0 < =" 0000 ";
If c 1=" 100 1 ",then c1< ="0000";
If c2=" 100 1 ",then C2 < =" 0000 ";
If c3=" 100 1 ",then C3 < =" 0000 ";
else c3 & lt= C3+ 1；
End if;
else c2 & lt= C2+ 1；
End if;
else c 1 & lt； = c 1+ 1；
End if;
else c0 & lt= c0+ 1；
End if;
End if;
End the process;
end rt 1；
3. Kilometer module
The process counting and charging pulse output are realized, and the block diagram is as follows:
Fig. 5 Block diagram of kilometer module
The source program is as follows:
Library ieee
Use IEEE.std _ logic _1164.all;
Use IEEE.std _ logic _ unsigned.all;
Entity Gong Li is
port(clk 1，start:in STD _ logic； -100 meter pulse
k 1，k2，k3，k4:out STD _ logic _ vector(3 down to 0)； -Mileage display
temp 2:out STD _ logic)；
End Gong Li;
Gong Li's architecture rt 1 Yes
Signal count _1:STD _ logic _ vector (3downto0);
Signal count _ 2: STD _ logic _ vector (3downto0);
Signal count _ 3: STD _ logic _ vector (3downto0);
Signal count _ 4: STD _ logic _ vector (3downto0);
begin
k 1 & lt； = count _ 1；
k2 & lt= count _ 2；
k3 & lt= count _ 3；
k4 & lt= count _ 4；
Process (start, clk 1)
begin
If(start='0') and then
count _ 1 & lt； ="0000";
count _ 2 & lt="0000";
count _ 3 & lt="0000";
count _ 4 & lt="0000"; Kilometers cleared
Elsif(clk 1' event and clk 1=' 1') and then
If (count _1= "1001") then-kilometer counter.
count _ 1 & lt； ="0000"; count _ 2 & lt= count _ 2+ 1； temp2 & lt=' 1';
If(count_2=" 100 1 ") then
count _ 2 & lt="0000"; count _ 3 & lt= count _ 3+' 1 '；
If(count_3=" 100 1 ") then
count _ 3 & lt="0000"; count _ 4 & lt= count _ 4+' 1 '；
End if;
End if;
other
count _ 1 & lt； = count _ 1+' 1 '； temp2 & lt='0';
End if;
End if;
End the process;
end rt 1；
4. Output module
In order to realize the output of all data, the component block diagram is as follows:
Fig. 6 Block diagram of output module
The source program is as follows:
Library ieee
Use IEEE.std _ logic _1164.all;
Use IEEE.std _ logic _ unsigned.all;
The physical book office is
port(y:in STD _ logic _ vector(3 down to 0)；
e:out STD _ logic _ vector(6 down to 0))；
End book office;
Shuchu architecture rt 1 for
begin
process
begin
Case y is
When "0000"= >; e & lt="0 1 1 1 1 1 1";
When "000 1"= >; e & lt="0000 1 10";
When "00 10"= >; e & lt=" 10 1 10 1 1";
When "00 1 1"= >; e & lt=" 100 1 1 1 1";
When "0100" = > e< = "110010";
When "0101"= > e< = "111";
When "0110" = > e< = "1111";
When "0 1 1 1"= >; e & lt="0000 1 1 1";
When "1000" = > e< = "1111";
When "1001"= > e< = "1100/1";
When others =>e & lt="0000000 ";
Close the case;
End the process;
end rt 1；
5. Display components
In order to display all data, the component block diagram is as follows:
Fig. 7 shows a block diagram of the module.
The source program is as follows:
Library ieee
Use IEEE.std _ logic _1164.all;
Use IEEE.std _ logic _ unsigned.all;
Entity stone is now
Port (start: in std_logic;
A: In STD _ logic _ vector (3downto0); -Select signal
c 1，c2，c3，c4，out 1，out2，out3，out 4:in STD _ logic _ vector(3 down to 0)； -Mileage display and time display input
y:out STD _ logic _ vector(3 down to 0))； -Mileage display, time display output
End the stone present;
The existing building rt 1 Yes
begin
process
begin
If(start='0') and then
y & lt="0000";
Otherwise, case a is
When "0000"= >; y & lt= c 1；
When "000 1"= >; y & lt= c2
When "00 10"= >; y & lt= c3
When "00 1 1"= >; y & lt= c4
When "0100" = > y < = out1;
When "0101"= > y < = out2.
When "0110" = > y < = out3.
When "0 1 1 1"= >; y & lt= out4
When others =>y<= "0000 ";
Close the case;
End if;
End the process;
end rt 1；
6.dian module
Figure 8 dian module block diagram
The source program is as follows:
Library ieee
Use IEEE.std _ logic _1164.all;
Use IEEE.std _ logic _ unsigned.all;
The entity point is
Port (a: in std_logic_vector (3 down to 0);
e:out STD _ logic)；
End code;
Dian's architecture rt 1 is.
begin
process
begin
Case a is
When "000 1"= >; e & lt=' 1';
When "0101"= > e< ='1';
When others =>E < =' 0';
Close the case;
End the process;
end rt 1；
Thirdly, the design and analysis of each module.
The overall top-level block diagram of the system is as follows:
System overall top-level block diagram
The ultimate function of the program is to realize waveform simulation.
1. Frequency dividing module
Since there are no clock signals of integer multiples of 14hz and 13hz in the experimental box, the frequency of 750khz is used for frequency division, so the clock frequencies of 14hz, 13hz and 1hz are approximately obtained. Drive the taxi through the above three pulse signals with different frequencies, and wait for different billing in two cases. The module elements are as follows:
Block diagram of frequency division module
The source program is as follows:
Library IEEE
Use IEEE.std _ logic _1164.all;
Use IEEE.std _ logic _ arith.all;
Use IEEE.std _ logic _ unsigned.all;
Entity separation is
Port (clk_750k: in std_logic; -System clock
clk _ 14:buffer STD _ logic； -14 frequency division
clk _ 13:buffer STD _ logic； -13 frequency division
clk _ 1:buffer STD _ logic)； -1 frequency division
End employment;
The architecture rt 1 is.
Signal q_ 14: integer range 0 to 53570; -define the intermediate semaphore
Signal q_ 13: integer range 0 to 57691;
Signal q_ 1: integer range 0 to 749999;
begin
Process (clk_750k)
begin
If (clk_750k' event and clk_750k=' 1'), then
If q_ 14=53570, then q _14 < =0; clk _ 14 & lt； = not clk _ 14；
else q _ 14 & lt； = q _ 14+ 1；
End if; -get 14hz frequency signal.
If q_ 13=5769 1, then q _13 < =0; clk _ 13 & lt； = not clk _ 13；
else q _ 13 & lt； = q _ 13+ 1；
End if; -get 13hz frequency signal.
If q_ 1=749999, then q _1< =0; clk _ 1 & lt； = not clk _ 1；
else q _ 1 & lt； = q _ 1+ 1；
End if; -obtain 1hz frequency signal.
End if;
End the process;
end rt 1；
2. Metering module
The metering module mainly completes the functions of timing and recording.
Timing part: calculate the cumulative waiting time of passengers. When the waiting time exceeds 2 minutes, the en 1 enable signal in this module becomes1; When each rising edge of clk 1 comes, the timer will automatically increment 1 with a range of 59min, and will automatically return to zero after full scale.
Log part: calculate the kilometers traveled by passengers. When the mileage exceeds 2km, the en0 enable signal in this module will become1; When each rising edge of clk comes, log will increase by 1, and the range of log is 99km, and it will automatically return to zero after full scale.
The component block diagram is as follows:
Block diagram of metering module
The analog waveform of the metering module is:
The source program is as follows:
Library ieee
Use IEEE.std _ logic _1164.all;
Use IEEE.std _ logic _ arith.all;
Use IEEE.std _ logic _ unsigned.all;
Entity Ji Liang is
Port (start: in std_logic; -billing start signal
Fin: in std_logic; -Mileage pulse signal
Stop: in std_logic; -Wait for the signal while driving.
Clk 1: in std_logic; -Driving pulse
en 1，en0:buffer STD _ logic； -billing unit price enable signal
k 1，k0:buffer STD _ logic _ vector(3 down to 0)； -mileage count
m 1，m0:buffer STD _ logic _ vector(3 down to 0))； -Wait time count
End Ji Liang;
The building rt2 in Ji Liang is
Signal w: integer range 0 to 59; -Timing range 0~59
begin
Process (clk 1)
begin
If (clk 1' event and clk 1=' 1'), then
If start='0', then
w & lt=0; en 1 & lt； ='0'; en0 & lt='0'; m 1 & lt； ="0000";
m0 & lt="0000"; k 1 & lt； ="0000"; k0 & lt="0000";
Elsif stop =' 1' and then time the start signal.
If w=59, then
w & lt=0;
else w & lt= w+ 1；
End if;
If m0=" 100 1 ",then
m0 & lt="0000";
If m 1="0 10 1 ",then
m 1 & lt； ="0000";
else m 1 & lt； = m 1+ 1；
End if;
else m0 & lt= m0+ 1；
End if;
If stop=' 1', en0 < =' 0';
if m 1 & amp； M0> "00000001"and then en1<; =' 1'; -If the waiting time is more than 2 minutes, en 1 is set to 1.
else en 1 & lt； ='0';
End if;
End if;
Elsefin =' 1' and then start to calculate the mileage.
If k0=" 100 1 ",then k0 < =" 0000 ";
If k 1=" 100 1 ",then k1< ="0000"; -Log range 0~99
else k 1 & lt； = k 1+ 1；
End if;
else k0 & lt= k0+ 1；
End if;
If stop='0', then
en 1 & lt； ='0';
If k1&; K0> Then "0000000 1"
en0 & lt=' 1'; -If the mileage is greater than 2km, en0 is 1.
else en0 & lt='0';
End if;
End if;
End if;
End if;
End the process;
End rt2
3. Control module
This module is mainly a process of selecting and outputting the pulses of 14hz and 13hz output by each frequency division module through two different input enable signals en0 and en 1 generated by the metering module. The module realizes the selection of double pulse; The ultimate goal is to calculate the price of different time periods in the driving process in the charging module.
The module elements are as follows:
Block diagram of control module
The analog waveform of the control module is:
The source program is as follows:
Library IEEE
Use IEEE.std _ logic _1164.all;
Use IEEE.std _ logic _ arith.all;
Use IEEE.std _ logic _ unsigned.all;
Entity control is
Port (en0, en 1: in std_logic; -Enable selection signal
clk _ in 1:in STD _ logic； -14 divided input signal
Clk_in2: in std_logic; -13 divided input signal
clk _ out:out STD _ logic)； -Output signal
Duan kongzhi;
The empty building rt3 is
begin
Process (en0, en 1)
begin
Ifen0 =' 1' and then-realize the function of choosing one from the other.
clk _ out & lt= clk _ in 1；
Elsefen1='1'and then
clk _ out & lt= clk _ in2
End if;
End the process;
End rt3
4. Charging module
When the charging signal start is always at a high level, that is, the charging state, the module charges different unit price periods according to the signal selected by the control module. That is, if the journey is within 2km and the cumulative waiting time is less than 2min, the starting price is 5 yuan; 2 kilometers away, it will be charged per kilometer 1.4 yuan, and if the accumulated time exceeds 2 minutes, it will be charged per minute 1.3 yuan. C0, c 1, c2 and c3 respectively indicate the display of expenses.
Module elements include:
Block diagram of billing module
The analog waveform of the charging module is:
The source program is as follows:
Library IEEE
Use IEEE.std _ logic _1164.all;
Use IEEE.std _ logic _ arith.all;
Use IEEE.std _ logic _ unsigned.all;
Qi Fei is an entity
Port (clk2: in std_logic; -Charging drive signal
Start: in std_logic; -billing start signal
c0，c 1，c2，C3:buffer STD _ logic _ vector(3 down to 0))；
Duan jifei;
Jifei's rt4 architecture is
begin
Process (clk2, start)
begin
If start='0', then C3 < = "0000"; c2 & lt="0000"; c 1 & lt； ="0 10 1"; c0 & lt="0000"; -Starting price 5 yuan.
Elsif clk2' event, and clk2=' 1'
If c0=" 100 1 ",then C0 < =" 0000 ";
If c 1=" 100 1 ",then c1< ="0000";
If c2=" 100 1 ",then C2 < =" 0000 ";
If c3=" 100 1 ",then C3 < =" 0000 "; -The appraisal range is 0~999.9.
else c3 & lt= C3+ 1；
End if;
else c2 & lt= C2+ 1；
End if;
else c 1 & lt； = c 1+ 1；
End if;
else c0 & lt= c0+ 1；
End if;
End if;
End the process;
End rt4
5. Display components
The display module completes the display of pricing, timing and log data. The billing data is sent to the display module for decoding, and finally sent to the corresponding digital tubes with units of 100 yuan, 10 yuan, yuan and angle for display. The timing data is sent to the display module for decoding, and finally sent to the digital tube corresponding to the division unit for display. The log data is sent to the display module for decoding, and finally sent to the digital tube with km as the unit for display.
Module elements include:
Display module block diagram
The source program is as follows:
Library ieee
Use IEEE.std _ logic _1164.all;
Use IEEE.std _ logic _ unsigned.all; -Define the library package
Define entities.
Port (
Clk_scan: in std_logic; -Scan clock signal port settings
C3, c2, c 1, c0: in std_logic_vector(3 downto 0); -Total cost input port
k0，k 1:in STD _ logic _ vector(3 down to 0)； -Mileage input port
m0，m 1:in STD _ logic _ vector(3 down to 0)； -latency input port
sel:out STD _ logic _ vector(2 down to 0)； -Digital tube position selection signal for controlling scanning signal output port.
led:out STD _ logic _ vector(6 down to 0)； -Control port of digital tube
Led _ DP:out STD _ logic- decimal point output port of digital tube.
);
End the stone present;
The building rt5 in Shixian is
Signal segment: STD _ logic _ vector (6 down to 0); -Digital display tube intermediate variable
Signal shuju: STD _ logic _ vector (3downto0); -Select the intermediate variable at the input.
Signal CNT: STD _ logic _ vector (2downto0); -Control the intermediate variable of the digital tube.
Small signal: std _ logic- intermediate variable of decimal point
begin
Process(clk _ scan)- Starts the process.
begin
If clk_scan event and clk_scan=' 1', then
cnt & lt= CNT+ 1； -Every time the scanning signal has a rising edge, 1 scanning is realized.
End if;
End the process; -End this process
Process (cnt)-Start the process (select Scan Display Digital Tube)
begin
Assign values to each digital tube during scanning.
When "000" = > Shuju < = C0
When "00 1"= >; Shuju < = c1;
When "0 10"= >; Shuju < = C2
When "0 1 1"= > Shuju < = C3.
When "100"= > Shuju < = k0.
When "10 1"= > Shuju < = k1;
When "1 10"= > Shuju < = M0.
When "11"= > Shuju < = m1;
When others = & gtnull
Close the case;
If (cnt="00 1 "or cnt=" 1 10")
Then small electricity & lt=' 1'; -Displays decimal points in mileage and total cost.
Else small electricity & lt='0';
End if;
End the process; -End this process
Shuju)-Start the process (decoding display)
begin
The case tree is
When "0000"= >; Segment & lt = "011111"; - 0
When "000 1"= >; Segment & lt="0000 1 10 "; - 1
When "00 10"= >; Segment & lt = "101101"; - 2
When "00 1 1"= >; Segment & lt = "100111"; - 3
When "0 100"= > segment < ="110010 "; - 4
When "0 10 1"= > segment & lt ="111"; - 5
When "0 1 10"= > segment & lt ="1111"; - 6
When "0 1 1 1"= >; Segment & lt = "0000111"; - 7
When "1000"= > segment & lt ="1111"; - 8
When "100 1"= > paragraph & lt ="111"; - 9
When others = & gtnull
Close the case;
End the process;
sel & lt= cnt
Led < = segment;
Led _ DP < = small power;
End rt5
Second, the course design work record:
Including: design steps and schedule, debugging steps and schedule, and description of project completion results.
2. Description of project completion results:
The starting price that this meter can realize is 5 yuan; The unit price 1 km required by the experiment is realized. When the driving distance is more than 2km, it will be charged per kilometer 1.4 yuan, and the mileage and total cost can be displayed. Drive 6 kilometers, wait for 4 minutes, and the fare will be displayed 15.8 yuan. The total cost of the calculation formula = starting cost+(mileage -2km) * mileage unit price+waiting time * and so on; That is15.8 = 5+(6-2) *1.4+4 *1.3. The experimental results are completely consistent with the theoretical results, and the experimental design is successful.